Low Power Near Threshold 10T SRAM Bit Cells with Enhanced Data Independent Read Port Leakage for Array Augmentation in 32nm CMOS
ABSTARCT :
The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and Ion/Ioff ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, datadependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce datadependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices.
EXISTING SYSTEM :
? A couple of options exist in order to enhance the strength of the access-devices relative to the load-devices.
? Although a variety of techniques, including parallelism and pipelining, exist in order to improve the performance of general logic (and promote voltage scaling), SRAM design is highly constrained by its structure and need to maximize density, hence requiring very different approaches.
? In all, a tight coupling exists between energy, performance, and density, and although their various interactions raise several limitations, they also increase the options for addressing target objectives.
DISADVANTAGE :
? Multiple supply line assist can also be used to improve read and write half-select stability issues in SRAMs.
? These issues have included the implementation of assist techniques, novel cell design, architectural improvements, or technological developments.
? Half-select and read-disturb issues in SRAMs can be mitigated by optimization of word-line voltage level.
? A process variation tolerant selective precharge assist has also been used to decrease bit-line voltage level using charge sharing to improve half-select disturb issues.
PROPOSED SYSTEM :
• A sense-amplifier is proposed that provides regenerative small-signal sensing.
• Due to the promise of single-ended bit-cells (e.g. 8T) for ultra-low-voltage, lowenergy applications, the sense-amplifier proposed provides variation resilient single-ended sensing.
• To overcome these limitations, alternate bit-cell topologies have been proposed that attempt to improve the low-voltage trade-offs and provide some additional voltage scalability.
• The target technology used to demonstrate the proposed techniques is 45nm LP CMOS, which highlights the variability associated with density maximization.
ADVANTAGE :
? Many techniques have been proposed to improve the single ended read sensing performance, the area overhead still remains large.
? Although these approaches have been successful at this task, these still suffer from large area or varying data-dependent performance.
? With a unique topology in each of the three cells’ read port, we obtain improved read access performance, low energy per access, and low area respectively, thereby enlarging the design and application gamut for memory designers in low power sensors and battery enabled devices.
? This form of hierarchical sensing does not compare to differential sensing in terms of both performance and array efficiency.
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