Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
Abstract : Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON , 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs.
? In existing system Magneto resistive random access memory(MRAM) is used as configuration bit.
? Configuration bits are received in serially from external memory in the power down case, then data will be loss in this case.
? In order to use this memory the inconsistency has been introduced in the implementation of look up table.
? However, nvSRAM substantially larger than the cell size of the SRAM, and the writing half of the selected disturbance RRAM cells is also difficult to avoid.
? However, MRAM's ROFF / RON small PRAM or RRAM, the serial / parallel magnetic junctions, seems low compared to the margin, or as a result of a large area.
? The problem can be solved by introducing nonvolatile memory (NVM) as the configuration bit.
? A low-power variation-tolerant nvLUT circuit to overcome the issues in the previous work.
? To resolve this issue, dummy RRAM cell, which is programmed to a mid-state resistance, is adopted as the reference resistor.
? The resistance state of MRAM (Magneto resistive random access memory) is small compare with RRAM to store the data in the form of resistance state in storage cell of a MRAM ,thus resulting in larger area due to serial parallel magnetic junctions.
• Proposed system will be random access memory (resistive RAM structure of a storage cell.
• RRAM cell is employed as a configuration bit to provide sufficient sense margin .
• Based on the logic in memory concept that is look up table design, which is the core building block in FPGAs, has been proposed with non volatility.
• However, the size of non volatile SRAM cell is remarkably larger than that of SRAM, and the write disturbance is also difficult to avoid for half-select RRAM cells, and also proposed eight input LUT.
? SRAM-based field-programmable gate arrays (FPGAs) have been widely used during the last decades.
? Because of its large ROFF/RON, 1T1R RRAM cell is used as a configuration bit and a reference resistor to provide sufficient sense margin against memory and logic variations.
? RRAM(Resistive random access memory)has larger Roff/Ron(Resistance state) ratio to store the data in their storage cell .
? RRAM cell has been used as the configuration bit in proposed and a reference resistor as been used to provide sufficient sense margin to read and write data.
? The area cost is decreased because no serial and parallel memory cell combinations are needed.
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