Concept, Design, and Implementation of Reconfigurable CORDIC
Abstract : This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for circular or for hyperbolic trajectories in rotation as well as vectoring-modes. It can, therefore, be used to perform all the functions of both circular and hyperbolic CORDIC. We propose three reconfigurable CORDIC designs: 1) a reconfigurable rotation-mode CORDIC that operates either for circular or for hyperbolic trajectory; 2) a reconfigurable vectoring-mode CORDIC for circular and hyperbolic trajectories; and 3) a generalized reconfigurable CORDIC that can operate in any of the modes for both circular and hyperbolic trajectories. The reconfigurable CORDIC can perform the computation of various trigonometric and exponential functions, logarithms, square-root, and so on of circular and hyperbolic CORDIC using either rotation-mode or vectoring-mode CORDIC in one single circuit. It can be used in digital synchronizers, graphics processors, scientific calculators, and so on. It offers substantial saving of area complexity over the conventional design for reconfigurable applications.
? In this paper, we study some of the existing CORDIC implementation techniques additionally recommend the use of CORDIC algorithm for conversions.
? The paper reviews the work on polar to rectangular and rectangular to polar conversion using CORDIC implementation and their optimization in the power consumption.
? In RSCE, as the HALO dopings are inserted at the drain and source, their dopants overlap in short channel systems, increasing the total density of dopants in the channel A 12-track implementation (2.4µm height) has been chosen, since this is the form factor used by the existing ARM R&D library.
? When the CORDIC functions, especially the higher order functions, are matched to applications a system design issue the real power of CORDICs and related algorithms can be exploited.
? The deal selection of standard cells is a cell-based sizing problem of each transistor.
? With the change to nanometer technology as transistor sizes shrink to 28 nm and below, a range of fundamentally new design challenges are not addressed in current VLSI EDA devices, including the issue of schematic synthesis and 3D transistor structure architectures for MOS technology.
? The impact of negative short-channel effects in transistors is rising, especially at and below the 28 nm technology, with the reduction of geometrical sizes.
• A basic design of reconfigurable CORDIC based on a unified CORDIC algorithm has been proposed recently.
• It is based on the generalized principle proposed in to include hyperbolic and linear trajectories along with the original circular trajectory of operation.
• The coordinate calculation matrices for circular and hyperbolic CORDICs differ by the sign of operands, and to realize that additions are to be replaced by subtractions and vice-versa.
• In order to exploit the efficiency of hand design while simplifying the design process, we propose a bottom-up approach to compilation for custom computing machines.
? The field-programmable gate array (FPGA) and application-specified integrated circuit (ASIC) implementations along with complexity and performance considerations of reconfigurable CORDIC.
? Several algorithms have been proposed for area-delay-efficient and power-efficient implementation of CORDIC algorithms, either for circular trajectory or for hyperbolic trajectory.
? The reconfigurable design of is found to involve high reconfiguration overhead and results in low hardware utilization efficiency.
? We present a methodology for the design of reconfigurable CORDIC to be used for rotation-mode and vectoring-mode in circular and hyperbolic trajectories.
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