A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography
ABSTARCT :
This paper presents a fixed-point reconfigurable parallel VLSI hardware architecture for real-time Electrical Capacitance Tomography (ECT). It is modular and consists of a front-end module which performs precise capacitance measurements in a time multiplexed manner using Capacitance to Digital Converter (CDC) technique. Another FPGA module performs the inverse steps of the tomography algorithm. A dual port built-in memory banks store the sensitivity matrix, the actual value of the capacitances, and the actual image. A two dimensional (2D) core multiprocessing elements (PE) engine intercommunicates with these memory banks via parallel buses. A Hardware-software codesign methodology was conducted using commercially available tools in order to concurrently tune the algorithms and hardware parameters. Hence, the hardware was designed down to the bit-level in order to reduce both the hardware cost and power consumption, while satisfying real-time constraint. Quantization errors were assessed against the image quality and bit-level simulations demonstrate the correctness of the design. Further simulations indicate that the proposed architecture achieves a speed-up of up to three orders of magnitude over the software version when the reconstruction algorithm runs on 2.53 GHZ-based Pentium processor or DSP Ti’s Delphino TMS320F32837 processor. More specifically, a throughput of 17.241 Kframes/sec for both the Linear-Back Projection (LBP) and modified Landweber algorithms and 8.475 Kframes/sec for the Landweber algorithm with 200 iterations could be achieved. This performance was achieved using an array of [2×2] × [2×2] processing units. This satisfies the real-time constraint of many industrial applications. To the best of the authors’ knowledge, this is the first embedded system which explores the intrinsic parallelism which is available in modern FPGA for ECT tomography.
EXISTING SYSTEM :
? Electrical Capacitance Tomography (ECT) is an effective technique to measure a process non-intrusively by reconstructing the 2D or 3D dielectric distribution of its different constituencies.
? This makes ECT a good candidate for several industrial applications such as two-phase flow monitoring, quality control in manufacturing industry, and corrosion detection.
? The assessment process of biomedical EIT has been discussed and investigated through the impedance imaging of the existent substances.
? EIT is very useful in the diagnosis sector of pulmonary problems but there is the absence of compactness in the existing system.
DISADVANTAGE :
? One problem is that the circuits involved in driving the signal from the chip can limit the operating frequency of the device and therefore affect the accuracy of the capacitance readings.
? A study was performed to compare three main methods for ECT forward problem modelling: sensitivity distribution, multiple linear regression (MLR) and electric field strength (ELS).
? Although ECT systems have proved to be successful due to their non invasiveness, there are several issues that hinder them from being completely reliable.
? One issue is the slow data acquisition time, where it can take several milliseconds to acquire the required data and convert it into a reconstructed image.
PROPOSED SYSTEM :
• In, a dedicated architecture for SPECT imaging using a scalable multicore on- Chip Architecture for on-chip communication was proposed.
• Extensive simulations indicate that the proposed architecture achieves a speed-up of up to three orders of magnitude over the software version when the reconstruction algorithm runs on 2.53 GHZ-based Pentium processor.
• We are only focus on processing unit for this proposed system with RGB format image processing.
• The parallel processing module is parallel like architecture which is composed of several similar adder/multiplier processing units.
ADVANTAGE :
? The relatively low performance of the system can be justified by the fact that the IMMs modules are mainly involved in data acquisition and electric current generation for the electrodes, rather than in the image reconstruction task itself.
? However, compared to FPGA, their performance was lower because of the frequency and randomness of memory access which was off-chip.
? These reconstruction algorithms usually require significant computation time making dedicated hardware algorithms necessary to achieve real-time performance.
? The advantage of such decomposition is to let the hardware scalable to handle various bit widths operation, in addition to improve the overall throughput of the algorithm.
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