Towards Efficient Modular Adders based on Reversible Circuits
Abstract : Reversible logic is a computing paradigm that has attracted significant attention in recent years due to its properties that lead to ultra-low power and reliable circuits. Reversible circuits are fundamental, for example, for quantum computing. Since addition is a fundamental operation, designing efficient adders is a cornerstone in the research of reversible circuits. Residue Number Systems (RNS) has been as a powerful tool to provide parallel and fault-tolerant implementations of computations where additions and multiplications are dominant. In this paper, for the first time in the literature, we propose the combination of RNS and reversible logic. The parallelism of RNS is leveraged to increase the performance of reversible computational circuits. Being the most fundamental part in any RNS, in this work we propose the implementation of modular adders, namely modulo 2n-1 adders, using reversible logic. Analysis and comparison with traditional logic show that modulo adders can be designed using reversible gates with minimum overhead in comparison to regular reversible adders.
? In the existing system of modulo adder uses the Universal gates concept and it consumes more area.
? With existent analog to digital converters (ADC) that directly convert analog inputs to residues encoded in the TC format, engineers and researchers are increasingly interested in modular adders for TC.
? In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said that the number, letter or word is being encoded. The group of symbols is called as a code.
? The digital data is represented, stored and transmitted as group of binary bits. This group is also called as binary code. The binary code is represented by the number as well as alphanumeric letter.
? The proposed modular adders, based on the thermometer and one-hot coding result in average improvements for delay, the circuit area, and energy consumption.
? However, TGs have the problem of voltage drop and high internal capacitances, due to the direct exposure of the junction capacitors to the signals which are passing TGs.
? It should be noted that some multi-input gates can be implemented using tree structures of 2-input gates without impacting the delay.
? Modular addition is the most important and frequent operation applied on the components of RNS, including arithmetic units in the channels as well as forward and reverse converters.
• It is demonstrated that the purposed PERES full adder is superior to the current partners in writing in terms of waste yields.
• The proposed adders are designed using novel digital circuits supported on specific features of OHC and TC.
• In the first level of the proposed OHR-based adder, NAND and NOR gates can be used instead of AND and OR gates.
• Although the representation of numbers with the OHC requires one more bit than with the TC, the delay and the occupied area of the proposed OHR adder design are better than those of the proposed TCR adder design, while the energy consumption is very close for the two approaches.
? In this paper, we propose the joint usage of these two unconventional computing approaches, Residue Number System and Reversible Computing, to achieve ultra-efficient computing paradigm for the emerging applications.
? RNS is used nowadays to achieve also energy-efficient and high-performance implementation of various emerging applications, such as deep neural networks, communication networks and cloud storage.
? Researchers in academia and industry believe that Moore’s law is ending, and even newly delivered deep-submicron transistors are not significantly more efficient than their previous generations.
? This number system has been applied to achieve parallel and efficient implementations for asymmetric cryptographic and digital signal processing (DSP).
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