Partially Parallel Encoder Architecture for Long Polar Codes
Abstract : Due to the channel achieving property, the polar code has become one of the most favorable error-correcting codes. As the polar code achieves the property asymptotically, however, it should be long enough to have a good error-correcting performance. Although the previous fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the huge hardware complexity required. In this brief, we analyze the encoding process in the viewpoint of very-large-scale integration implementation and propose a new efficient encoder architecture that is adequate for long polar codes and effective in alleviating the hardware complexity. As the proposed encoder allows high-throughput encoding with small hardware complexity, it can be systematically applied to the design of any polar code and to any level of parallelism.
? Polar code is a new class of error correcting codes that provably achieves the capacity of the underlying channels. In addition concrete algorithms for constructing, encoding and decoding the code are all developed.
? Due to the channel capacity achieving property, the polar code is now considered as a major breakthrough in coding theory, and the applicability of the polar code is being investigated in many application including data storage devices.
? The polar code utilizes the channel polarization phenomenon that each channel approaches either a perfectly reliable or a completely noisy channel as the code length goes to infinity over a combined channel constructed with a set of N identical sub-channels.
? These problems, enabling high-speed, robust communications using polar codes.
? More Hardware complexity
? More Power dissipation
? Not support for long polar codes
• The process of encoding and decoding has been analyzed for VLSI implementation and an advanced architecture required for long polar codes has been proposed with reduced hardware complexity.
• The proposed approach and how to transform the architecture, a 4-parallel encoding architecture for the 16-bit polar code is exemplified in depth.
• Many optimization techniques have been applied to derive the proposed architecture.
• In the proposed system of 4 parallel architecture of polar code to be re-modified and to implement 8-parallel architecture of polar code, and finally show the same power consumption, and the report of area, delay and logic sizes.
? An architecture that can efficiently deal with long polar codes is necessary to make the very-large-scale integration (VLSI) implementation feasible.
? Although the polar code achieves the underlying channel capacity, the property is asymptotical since a good errorcorrecting performance is obtained when the code length is sufficiently long.
? The fully parallel encoder is intuitively designed based on the generator matrix, but implementing such an encoder becomes a significant burden when a long polar code is used to achieve a good error-correcting performance.
? The higher parallel architecture has advantages of small latency and high encoding throughput.
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