A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications
ABSTARCT :
Single-stage regulator topologies are often preferred in embedded applications due to their low power consumption with a single-pole behavior, resulting in easy frequency compensation. Since the achievable differential gain from a single stage is low, the dc load regulation is poor over a wide dynamic range. This paper presents a single-stage, adaptively biased, low-dropout regulator to achieve a comparable dc load regulation similar to multistage topologies. This is achieved mainly by modifying the adaptive bias loop which amplifies both the common-mode and differential-mode signals. In addition, as the proposed regulator is stable for a wide range of output capacitors, including the capacitor-less (on-chip) and with-capacitor (off-chip) conditions, it is suitable for more generic applications. The proposed regulator is implemented in a standard 0.18-µm CMOS technology. The experimental results show that the regulator is capable of delivering up to 100 mA with a dc load regulation of 0.140 mV/mA and is stable with Co = 3.3 nF (capacitor-less) and Co = 1 µF (with-capacitor).
EXISTING SYSTEM :
? Several techniques for generating accurate output currents exist. The simplest uses a single resistor in the ground return lead.
? Several options exist for the desktop computer system designer.
? Another is to use the existing high current 5V supply and employ a low dropout (LDO) linear regulator to provide 3.3V.
? The heat sink should be mounted so that at least 0.25 inches (about 6mm) of separation exists between the sides and top of the sink and other components or the system case.
? Existence of a shorted output is continually monitored; the system will protect the pass device for an indefinite time.
DISADVANTAGE :
? The key issue of developing a generic LDO topology is the tradeoff between the dc accuracy and the loop stability.
? The only way to mitigate this issue is to increase the size of the pMOS power transistor.
? The simplest, lowest cost solution for this problem is the modern, very low dropout version of the venerable linear regulator.
? This circuit has a number of problems, including poor stability (a large output capacitor is required to squelch oscillations), poor current limiting characteristics, poor load transient response, no over temperature shutdown protection, and requires numerous external components.
PROPOSED SYSTEM :
• A low-dropout regulator (LDO) with 800 mA load current with wide range input voltage is designed and proposed in this paper.
• The proposed regulator is stable for a wide range of logics with variable capacitors and also for the capacitor-less conditions.
• The stability of the proposed LDO regulator is achieved by three diferent compensation techniques including Miller, cascode, and Q-reduction.
• The load and line transient responses of the proposed LDO regulator are simulated to verify the stability and evaluate the transient performance.
• It is worth mentioning that the proposed regulator consumes only a quiescent current of 1.83 µA at small load current.
ADVANTAGE :
? Based on the critical dynamic performance requirement of different blocks, one may need multiple instances of both the categories in a single chip.
? The different performance metrics vary widely in various applications based on their input–output voltage/current ranges, compensation strategy, adopted technology for implementation, and so on.
? Therefore, a figure of merit (FOM) may reasonably reflect the tradeoff performance but does not universally hold good.
? Due to the unavailability of the other performance parameters, we are not in a position to compare them.
? Moreover, the proposed regulator consumes a lowquiescent current at no-load condition without significantly degrading the current efficiency ?c at maximum load current.
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