HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic
ABSTARCT :
AQFP (adiabatic quantum-flux-parametron) circuits are currently verified by analog-based simulation, which would be an obstacle for large-scale circuits design. In this paper, we present a logic simulation model for AQFP logic. We made a functional model based on a finite-state machine approach using a hardware description language (HDL), which enables the simulation of large-scale AQFP circuits using commercially available logic simulation tools. We have developed a library for logic simulation and implemented an 8-bit carry look-ahead adder, which is composed of over 1000 Josephson junctions (JJs). We also include timing information in our logic simulation models for timing analysis. Since the library is based on a parameterized approach, it can be easily modified for different fabrication technologies and low-level circuit parameters.
EXISTING SYSTEM :
? We have investigated this on AQFP buffer chains and found that incorrect output occurs when the excitation current is delayed by a certain period which means a timing window exists between input current (input) and excitation current (clock).
? Though it is in existence for more than two decades, still, its full potential has not been explored.
? The design of adiabatic circuits requires much more efforts in contrast to the non-adiabatic logic for which well-developed tools exist.
? The future scope exists in developing an energy model such that the energy consumption of any 4-phase adiabatic logic families can be fairly approximated before the design of the circuits at transistor level are performed.
DISADVANTAGE :
? The significant amount of energy consumption has become a critical problem in modern society, and arouses us of the urgent requirement for energy-efficient computing technologies.
? Although excitation currents serve as clocks and synchronize the AQFP logic gates, timing issues still exist due to clock skews and signal delay, especially when the circuit scale becomes large.
? This will lead to an increasing static power as the circuit scale expands, and makes power dissipation a disadvantage of RSFQ.
? The proposed HDL model can easily identify the errors caused by the complementary inputs when both are at logic ‘0’, which the SPICE simulation fails to identify.
PROPOSED SYSTEM :
• Adiabatic Quantum-Flux-Parametron (AQFP) logic is an adiabatic superconductor logic family that has been proposed as a future technology towards building extremely energy-efcient computing systems.
• In order to mitigate the power consumption overhead of DC bias, the Adiabatic Quantum-Flux-Parametron (AQFP) technology has been proposed using AC bias/excitation currents as both (multi-phase) clock signal and power supply.
• Te proposed energy consumption estimation methodology is accurate and specifcally designed for AQFP circuits.
• We have proposed a design flow for AQFP VLSI circuit design, which includes logic synthesis, semi-automatic routing and HDL-based back-end verification.
ADVANTAGE :
? Adiabatic quantum-flux-parametron (AQFP) logic is one kind of novel superconductor logic offering extremely high-energy efficiency for building high-performance computing systems.
? It is easy to invert a normal input by negating the coupling coefficient of the output transformer of the logic gate without any other cost, which is an attractive feature of the AQFP logic family.
? However, the static energy dissipated from the dc-bias current flowing through bias resistors eliminates the advantage of superconducting circuits when integrated to system scales.
? The HDL-state ‘x’, which is the undetermined state, is used to describe the random output of an AQFP gate.
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