An Efficient VLSI Architecture for Convolution Based DWT Using MAC
ABSTARCT :
The modern real time applications related to image processing and etc., demand high performance discrete wavelet transform (DWT). This paper proposes the floating point multiply accumulate circuit (MAC) based 1D/2D-DWT, where the MAC is used to find the outputs of high/low pass FIR filters. The proposed technique is implemented with 45 nm CMOS technology and the results are compared with various existing techniques. The proposed 8 × 8-point floating point 2-levels 2D-DWT achieves 27.6% and 83.7% of reduction in total area and net power respectively as compared with existing DWT.
EXISTING SYSTEM :
? The lifting scheme represents the fastest implementation of the DWT than the existing convolution based DWT.
? When comparing to several existing neural network architectures and learning algorithms, Kohonen’s self-organizing map (SOM) is one of the most popular neural network models.
? Moreover, it has small output latency of nine cycles and does not require control signals which are commonly used in most of the existing DWT structures.
? First Generation Structured ASICs provided designers with considerable power and cost improvements over FPGAs but failed to remove many barriers to entry that existed with traditional cell-based ASICs.
DISADVANTAGE :
? The artificial neural network results with solutions whose performance is better than that of traditional problem solving methods, and also provides a clear understanding of human cognitive abilities.
? Image Compression addresses the problem of reducing the amount of data required to represent an image or video.
? Both disadvantages were due to the two levels of configurable logic, because programmable logic planes were difficult to manufacture and introduced significant propagation delays.
? The MAC operation can be defined as multiplication and repeated addition.
PROPOSED SYSTEM :
• This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floatingpoint arithmetic operations.
• The proposed design has lesser depth than a conventional floatingpoint MAC as well as a lower area requirement than other ways of floating point MAC implementation, both with/without a pipeline.
• The lifting scheme entirely relies on the spatial domain, has many advantages compared to filter bank structure, such as lower area, power consumption and computational complexity.
• The lifting scheme can be easily implemented by hardware due to its significantly reduced computations.
ADVANTAGE :
? The major objective of this work is to improve the performance of the DWT for DSP applications.
? In image processing, DWT can be used in image compression, image reconstruction, image coding, and image fusion.
? The lifting based parallel architectures are the transpose buffer is not used and the critical path delay equal to two adders and one multiplier.
? In proposed floating point 1D/2D-DWT implementation, one proposed floating point MAC is used in each filter of the row/column process.
? The critical path delay of is less than others, because the multipliers used in are inner pipelined.
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