A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor Redundance
Abstract : With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper is focused on designing combinational circuits for soft error tolerance with minimal area overhead. The idea is based on analyzing random pattern testability of faults in a circuit and protecting sensitive transistors, whose soft error detection probability is relatively high, until desired circuit reliability is achieved or a given area overhead constraint is met. Transistors are protected based on duplicating and sizing a subset of transistors necessary for providing the protection. In addition to that, a novel gate-level reliability evaluation technique is proposed that provides similar results to reliability evaluation at the transistor level (using SPICE) with the orders of magnitude reduction in CPU time. LGSynth’91 benchmark circuits are used to evaluate the proposed algorithm. Simulation results show that the proposed algorithm achieves better reliability than other transistor sizing-based techniques and the triple modular redundancy technique with significantly lower area overhead for 130-nm process technology at a ground level.
? Reliability of a circuit can be defined as its ability to function properly despite the existence of such errors.
? It describes and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor style designs.
? In the existing system, the Triple modular redundancy (TMR), a popular and widely used technique is used, it creates three identical copies of the system and combines their outputs using a majority voter.
? The existing transistor sizing techniques, the proposed algorithm incurs significantly less area overhead with better reliability measures.
? The impact of the proposed algorithm on the area and reliability of LGSynth’91 benchmarks, which consist of circuits with varying complexity in terms of area, number of inputs, and outputs.
? The use of ip-chip packaging and multiple levels of metals will further exacerbate the problem.
? The fact that commercial manufacturers must deal with SEE concerns will provide a collateral benefit to the radiation effects community as more resources are brought to bear on the problem.
? The SET have a major impact on circuit operation, and they should be treated properly.
• The proposed algorithms are used to protect sensitive transistors whose probability of failure is relatively high and to compute the circuit failure rate/reliability at the gate level.
• In this paper, a generalized modular redundancy (GMR) scheme to enhance the reliability of combinational circuits is proposed.
• In this paper, we have proposed an STR-based fault tolerance technique for combinational circuits.
• This paper proposed a design of combinational circuits for soft error tolerance with minimal area overhead.
• We proposed selective-transistor redundancy algorithm that protects individual sensitive transistors of a circuit.
? Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate.
? Triple modular redundancy (TMR), a popular and widely used technique, creates three identical copies of the system and combines their outputs using a majority voter.
? The library used for mapping consists of an inverter and two-, three-, and four-input NAND and NOR gates.
? This clearly indicates that the proposed method is scalable and can be used to further improve other techniques.
? While very effective, passive feedback elements reduce circuit performance and degrade IC manufacturability.
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