Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Abstract : The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption with the goal of maintaining a particular Peak Signal-to-Noise Ratio (PSNR) threshold for any video. Toward this end, we design reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the characteristics of each individual video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of 1%–10%) across different videos while achieving a power saving up to 38% over a conventional nonapproximated MPEG encoder architecture. Note that although the proposed reconfigurable approximate architecture is presented for the specific case of an MPEG encoder, it can be easily extended to other DSP applications.
 EXISTING SYSTEM :
 ? In order to diminish the time-taking of the intermediate products of the adder stages of multipliers, for providing high speed and lower power consumption with minimized area, Compressors are equipped instead of regular Adders. ? However, existing approximate architectures typically fix the level of hardware approximations statically and are not adaptive to input data. ? There also exist instances of approximations introduced in an MPEG encoder. ? Logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling is demonstrated.
 DISADVANTAGE :
 ? This paper adopts a different approach to addressing this problem by dynamically reconfiguring the approximate hardware architecture depending on the inputs. ? The approximation is actually a joint combinatorial optimization problem, i.e., approximations introduced in both DCT and ME modules interact and influence output video quality together. ? However, such a conservative approach will, as expected, drastically impact the power savings as well. ? Other drawbacks include the power and area overheads required to construct the feedback controller and a number of extra logical blocks, like magnitude comparators, registers, that will eat up a large part of the savings we have achieved from the RABs.
 PROPOSED SYSTEM :
 • We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the Characteristics of each individual video. • Most approximate hardware architectures proposed so far suffer from the limitation that, for Widely varying input parameters, it becomes very hard to provide a quality bound on the output, and in some cases, the output quality may be severely degraded. • An adaptive bit masking method is proposed in , where the authors propose to truncate the pixels of the current and previous frames required for ME depending upon the quantization step. • We proposed a reconfigurable approximate architecture for the MPEG encoders that optimize power consumption while maintaining output quality across different input videos.
 ADVANTAGE :
 ? There has been a lot of effort in constructing energy-efficient video compression schemes. ? In reality, the curves will actually be pentadimensional in nature; however, efficient pruning of the search space can be done due to the sustained inverse relationship between quality degradation and the weights. ? The complexity of extracting the optimal weights can be significantly reduced with the help of an efficient heuristic. ? This takes advantage of the spatial locality of low SAD values at or near the target MB block in the current frame. ? However, it also increases the complexity of the decoder block used for asserting the right select signals to the multiplexers as well as the logic overhead for the multiplexers themselves.

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