Probability Driven Multi bit Flip-Flop Integration with Clock Gating
Abstract : Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design techniques that are usually treated separately. Combining these techniques into a single grouping algorithm and design flow enables further power savings. We study MBFF multiplicity and its synergy with FF data-to-clock toggling probabilities. A probabilistic model is implemented to maximize the expected energy savings by grouping FFs in increasing order of their data-to-clock toggling probabilities. We present a front-end design flow, guided by physical layout considerations for a 65-nm 32-bit MIPS and a 28-nm industrial network processor. It is shown to achieve the power savings of 23% and 17%, respectively, compared with designs with ordinary FFs. About half of the savings was due to integrating the DDCG into the MBFFs.
? In existing system power reduction is achieved by using clock gating.
? With clock gating, the Clock signals are multiply with an AND gate logic to explicitly predefined enabling signal. But this clock gating still leaves large number of redundant clock pulses.
? Although substantially increasing design productivity, such tools require the employment of a long chain of automatic synthesis algorithms, from register transfer level (RTL) down to gate level and net list.
? Development of automatic and effective methods to reduce this inefficiency is desirable. In the sequel, we will use the terms toggling, switching, and activity interchangeably.
? The 2-MBFF merging is formulated as an optimization problem that aims at maximizing the number of merged FFs.
? Using toggling correlations for MBFF grouping has the drawback of requiring early knowledge of the value change dump vectors of a typical workload.
? That issue for Flip Flops combining yields maximum toggling0correlation, and consequently maximal power0savings, has been demonstrated as0NP-hard.
? Its drawback is the requirement of early knowledge of Value Change Dump (VCD) vectors, derived from many power simulations representing the typical operation and applications of the design in hand.
• Our work proposes a systematic, toggling probability-driven MBFF grouping algorithm, provably maximizing the expected energy savings.
• The proposed MBFF design flow has been used for a 32-bit pipelined MIPS processor, implemented in TSMC 65nm process technology.
• In an attempt to reduce the overhead, it is proposed to group several FFs to be driven by the same clock signal, generated by bring the enabling signals of the individual FFs.
• Multi-bit Flip-Flop method is to eliminate the total inverter number by sharing the inverters in the flip-flops. Data driven clock gating reduce redundant clock pulses.
? MBPL clock power was minimized by taking advantage of pulsed-latch timing behavior that is similar to a FF, and its time-borrowing capabilities similar to a latch.
? More common information is the average toggling bulk probability of each FF in the design, which the following discussion takes advantage of in deriving an optimal toggling probability-driven FFs grouping.
? A power savings model utilizing MBFF multiplicities and FF toggling probabilities is developed, which was then used by the algorithm in a practical design flow.
? The FF clustering approach presented in has later been used in for replacement of 1-bit FF with Multi-Bit Pulsed-Latch (MBPL) in the physical layout.
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