A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell
ABSTARCT :
A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of 1.4× and 1.28× as that of isoarea 6T and read-decoupled 8T (RD-8T), respectively, at 300 mV. The standard deviation of write SNM for 8T cell is reduced to 0.4× and 0.56× as that for 6T and RD-8T, respectively. It also possesses another striking feature of high read SNM ~2.33×, 1.23×, and 0.89× as that of 5T, 6T, and RD-8T, respectively. The cell has hold SNM of 1.43×, 1.23×, and 1.05× as that of 5T, 6T, and RD-8T, respectively. The write time is 71% lesser than that of single-ended asymmetrical 8T cell. The proposed 8T consumes less write power 0.72×, 0.6×, and 0.85× as that of 5T, 6T, and isoarea RD-8T, respectively. The read power is 0.49× of 5T, 0.48× of 6T, and 0.64× of RD-8T. The power/energy consumption of 1-kb 8T SRAM array during read and write operations is 0.43× and 0.34×, respectively, of 1-kb 6T array. These features enable ultralow power applications of 8T.
EXISTING SYSTEM :
? The power consumption can be minimized by using nonconventional device structures, new circuit topologies and optimizing the various architectures.
? The portable microprocessor controlled devices contain embedded memory which represents an extensive part of the system on chip (SoC).
? Ultra-low power on chip memory is now mandatory to achieve higher reliability and longer battery life for handheld devices.
? The SEDFC enables writing through single nMOS in 8T and it also separates the read and write path.
DISADVANTAGE :
? The data stability of SRAM cell is a severe problem and worsens with the scaling of MOSFET to sub nanometer technology.
? The basic and an effective way to eliminate this problem is the decoupling of true storing node from the bit lines during the read operation.
? Another problem is to obtain optimized noise margin against process variations at all operations.
? Although, voltage scaling has led to circuit operation in subthreshold regime with minimum power consumption, but there is a disadvantage of exponential reduction in performance.
PROPOSED SYSTEM :
• The proposed single finished with dynamic criticism control 8T static RAM (SRAM) cell improves the static commotion edge (SNM) for ultralow control supply.
• Due to the design constraints and contact area between M2, M3, M4, and M8 for proposed 8T, there is 2× area overhead as compared with 6T cell.
• The proposed 8T cell has high stability and can be operated at ULV of 200–300 mV power supplies.
• The advantage of reduced power consumption of the proposed 8T cell enables it to be employed for battery operated SoC design.
ADVANTAGE :
? The single-ended design is used to reduce the differential switching power during read–write operation.
? A separate read bit line (RBL) is used to transfer the data from cell to the output when read word line (RWL) is activated. Input data and column address signals are used to generate these control signals.
? A common circuit is used for a single column, therefore, there would be a small area overhead at array level.
? An 8T-SRAM cell using Adoptive Voltage Level Ground (AVLG) technique with better performance, low power consumption and less leakage power has been implemented.
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