Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
Abstract : Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs). Nevertheless, when using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay. Different codes have been proposed to tolerate MCUs. For instance, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column–line–code (CLC) has been designed to tolerate MCUs in space applications. CLC is a modified Matrix code, based on extended Hamming codes and parity checks. Nevertheless, a common property of these codes is the high redundancy introduced. In this paper, we present a series of new lowredundant ECCs able to correct MCUs with reduced area, power, and delay overheads. Also, these new codes maintain, or even improve, memory error coverage with respect to Matrix and CLC codes.
? Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density.
? The probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments.
? One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs).
? When using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay.
? The MCU problem must be taken into account for the design of the corresponding fault tolerance methods, as space is an aggressive environment subjected to the impact of high-energy cosmic particles.
? The main problem when memory systems employ an ECC is the redundancy required.
? We want focus on long burst errors, which are expected to have more and more impact on space systems.
? Their main drawback is that only one bit in error can be corrected. Nevertheless, for common data word lengths, Hamming codes can detect some double error patterns, in addition to the SEC.
• The implementation and evaluation of the Data Segmentation Section Code (DSSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation.
• DSSC is an ECC based on two dimensional (2D) codes, that aims to correct and detect MCUs in memories.
• The proposed Data Segmentation Section Code (DSSC) an error detection/correction code for memory devices subjected to multiple cell upsets (MCUs). is based on parity codes and interleaving techniques to deal with several patterns of MCUs.
? The Matrix code implemented in this paper presents better correction and detection performance than an extended Hamming code, as it is able to correct all single errors and to correct or to detect all 2-bit burst errors.
? Our codes are very efficient to tolerate burst errors of from 2- to 4-bit length. Beyond 4-bit burst errors, the performance of our codes decreases notably due to their low redundancy.
? We can observe also that CLC performance is the worst from single errors up to 4-bit burst errors length.
? In this way, by using the tool, we can generate the parity check matrix of an ECC in an automatic and efficient way, just defining its error detection and/or correction capabilities.
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