Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
ABSTARCT :
The approximate computing paradigm emerged as a key alternative for trading off accuracy and energy efficiency. Error-tolerant applications, such as multimedia and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level.
The automatic detection of R-peaks in an electrocardiogram (ECG) signal is the essential step preceding ECG processing and analysis. The Haar discrete wavelet transform (HDWT) is a low-complexity pre-processing filter suitable to detect ECG R-peaks in embedded systems like wearable devices, which are incredibly energy constrained.
This work presents an approximate HDWT hardware architecture for ECG processing at very high energy efficiency. Our best-proposal employing pruning within the approximate HDWT hardware architecture requires just seven additions.
The use of a truncation technique to improve energy efficiency is also investigated herein by observing the evolution of the signal-to-noise ratio and the ultimate impact in the ECG peak-detection application. This research finds that our HDWT approximate hardware architecture proposal accepts higher truncation levels than the original HDWT.
In summary: Our results show about 9 times energy reduction when combining our HDWT matrix approximation proposal with the pruning and the highest acceptable level of truncation while still maintaining the R-peak detection performance accuracy of 99.68% on average.
EXISTING SYSTEM :
NEW and significant challenges driven by the energy efficiency concerns have been emerging across most internet of things applications. Edge computing overcomes or reduces the necessity of transmitting data to produce results, thus saving communication energy and reducing the dependence on data centers by sending compact data or just decisions taken at the edge. Batteries combined with energy-harvested systems generally sustain biomedical wearable and implantable devices that are extremely energy-constrained.
Notably, medical wearable devices have to guarantee a significant accuracy of electrocardiogram (ECG) processing. Therefore, biomedical algorithm kernels processing at the edge must be carefully implemented within dedicated hardware architectures, preferably using ultra-low-power VLSI design techniques to ensure its sustainability
Automatic detection of the R-peaks in the ECG signal is the essential step preceding ECG processing and analysis in industrial-strength biomedical applications. R-peak detection task is an intrinsically approximate operation with a binary result (i.e., true/false). Therefore, there is an ample design space for exploring different approximate computing techniques.
The Haar discrete wavelet transform (HDWT) is a low-complexity pre-processing algorithm suitable to detect ECG R-peaks in low-power embedded systems. Therefore, the critical challenge addressed in this work is how to reduce power dissipation in the HDWT hardware design.
Approximate computing has emerged as a key alternative for leveraging energy efficiency for most applications capable of tolerating errors from hardware, as if they were just another noise source. Error-tolerant applications such as video and signal processing, can process the information with lower-than-standard accuracy at the circuit-level while still performing, within the overall application, at an acceptable quality for the user.
Recently, approximate transforms have been emerging as an alternative to reduce the complexity of its hardware. However, most of the literature’s transform approximations have been proposed for multimedia processing, lacking ECG processing solutions.
In this work, we present the first approximate HDWT VLSI hardware architectures which combine coefficient approximation, pruning, and truncation. We investigate at design-time the approximate HDWT demonstrating the reduction in circuit area and power dissipation with a consequent trade-off in signal-to-noise-ratio (SNR).
Despite the lower SNR, our proposal fulfills the ultimate quality performance at the application-level with a slight improvement in the accuracy of the R-peak detection performance while providing a reduction of about 9 times in the energy required to process ECG signals. Our contributions presented in this paper are as follows:
DISADVANTAGE :
Overcome the necessity of transmitting data to produces results.
More energy constrained.
More logic sizes.
PROPOSED SYSTEM :
The methodology of approximation computing emerged as an ideal approach that allowed for the transfer of accuracy and energy efficiency. Error-tolerant programmes, which include signal processing and multimedia processing, are able to process the information with an accuracy that is lower than the norm while still satisfying a high and appropriate service quality at the application level.
The important phase that comes just before the processing and analysis of an electrocardiogram (ECG) data is the automated recognition of R-peaks within the ECG signal. The Haar discrete wavelet transform (HDWT) is a low-complexity pre-processing filter that is appropriate for detecting ECG R-peaks in embedded systems such as wearable devices, which are subject to very stringent energy constraints.
In this study, an approximate HDWT hardware architecture for ECG processing is presented with MIT-BIH Database. The energy efficiency of this design is quite good.
Only 7 improvements are necessary for our top suggestion, which involves doing pruning inside the basic concept of the HDWT hardware design. The use of a truncation technique to improve energy efficiency is also investigated in this article by observing the development of the signal-to-noise ratio and the ultimate impact in the ECG peak-detection application.
The proposed approach of this work gather about the effectiveness of the technique based on HDWT approximation hardware design approach using XOR MUX Full adder design instead of Conventional Full Adder design, and also design with higher levels of truncation than the normal HDWT.
When we combined our HDWT matrix approximation proposal with the pruning and the highest acceptable level of truncation, our results showed a reduction in energy consumption that was approximately nine times greater than the previous level. Finally this work developed in Verilog HDL, and Synthesized on Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.
In a conventional digital circuit design, one usually assumes that the system will provide accurate results, even under fixed bit-width arithmetic operations. However, in practice, the operations with a high level of accuracy are not always necessary, as even the analog-to-digital conversion at the start already computes approximate data wrt the physical phenomenon.
In many applications, digital circuits can generate good enough results, instead of the most accurate results, without compromising the functioning of the application in the system as a whole.
The approximate computing paradigm emerges as a solution to exchange precision, or quality of results, for a reduction in power dissipation, energy consumption, and area in the VLSI circuit.
ADVANTAGE :
Increases the necessity of transmitting data to produces results.
less energy constrained.
Reduced logic sizes using XOR-MUX Full Adder.
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