VLSI IMPLEMENTATION OF EFFICIENT IMAGE WATERMARKING ALGORITHM
ABSTARCT :
Protection and authentication of digital multimedia content during transmission has become very important with the ongoing development in communication and networking field. Aiming at this popular research topic of recent time, this paper presents a comparative analysis of different watermarking techniques performed in MATLAB. It also presents a robust VLSI architecture for watermarking which survives most of the attacks to which data is exposed on internet and contributes towards anti-plagiarism rule. This paper exhibits the ASIC implementation of an efficient digital watermarking algorithm for images based on frequency domain Discrete Wavelet Transform and spatial domain bit plane slicing.
EXISTING SYSTEM :
? The proposed architecture is designed aiming at easy integration into any existing digital camera framework.
? The proposed watermarking chip can be easily incorporated as a module in any existing JPEG encoder and a secured JPEG encoder can be developed.
? The proposed watermarking chip can also be directly integrated with any existing digital still camera.
? It is assumed that the proposed chip is to be used as a module in any existing JPEG encoder or a digital camera, and use their memory.
? The watermarking chip can also be integrated in any existing JPEG encoder.
DISADVANTAGE :
? The problem of receiving the multidigit decimal value is solved by using the Pixel Value Combiner which combines the multidigit decimal value and store in the RAM.
? One of the problems of memory initialisation in hardware descriptive languages like Verilog and VHDL is that, the constructs used for such initialisations are not synthesisable.
? With rapid increase in use of internet and digital media, transmission and reproduction of digital products has become very convenient but it has some drawbacks.
PROPOSED SYSTEM :
• The proposed algorithm is this paper works by manipulating the bits of base image pixels according to the respective pixel of watermark.
• One of the IP core used in the proposed architecture is Block Memory generator.
• In this paper, we propose a VLSI architecture that can insert visible watermarks in images.
• The signal-to-noise ratio (SNR) of the watermarked images obtained using the proposed chip and also of the watermarked images obtained using software schemes.
• The SNR in both hardware and software schemes found to be approximately same; thus, proving effectiveness of the proposed chip.
ADVANTAGE :
? Digital watermarking performed in spatial-domain consists of easy operations and are generally computational cost efficient but gives poor results after common signal processing like filtering and JPEG etc. and also after geometric distortions like scaling and cropping etc.
? Many researchers are trying to develop a memory, area and power efficient hardware implementation of watermarking algorithm.
? In this process the original gray scale image is transformed using frequency domain DWT to obtain HH, HL, LL, LH coefficients and then watermark is inserted in the suitable coefficients of transformed host image using spatial domain bit plane slicing.
? The paper also proposes and implements an efficient digital image watermarking architecture using a combination of spatial domain bit plane slicing and frequency domain Haar based DWT in VLSI.
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