A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits
ABSTARCT :
Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.
EXISTING SYSTEM :
? These codes can decode in a unique way up to n-k 2 errors, and there exists the possibility to decode them beyond the classical bounded radius n-k 2 .
? The decoding speed is a very important factor since one wants to optimize communications speed, but there exist contexts in which the use of such a decoding is not as important since the use of the algorithm is only causal in the overall process.
? The inferred codes have a similar number of equality check bits as existing SEC codes and in this manner don't require extra cost regarding memory or registers.
? This is more powerful than using two separate SEC codes (one for the data bits and the other for the control bits) as this requires additional uniformity check bits.
DISADVANTAGE :
? One problem that occurs when protecting the data in networking applications is that, to facilitate its processing, a few control bits are added to each data block.
? The main problem in using an extended SEC code is that the decoding of the control bits is more complex.
? The problem is that now, to decode the 3 control bits, we need to compute the 8 parity check bits and compare the results against the columns of the control bits.
? The proposed codes do have an impact on the decoding delay for the data bits. For the decoders, the added delay on data bits is significant for most word sizes.
PROPOSED SYSTEM :
• One of the objectives of this article is to study color attacks and propose adequate robustness measures.
• Therefore the proposed algorithm uses middle frequencies for the insertion of the mark as both invisibility and robustness against low pass filter attacks is required in such an algorithm.
• To assess the advantages of the proposed plot, a few codes have been actualized and contrasted and least weight SEC codes.
• The proposed codes are valuable in applications, where a couple of control bits are added to every datum square and the control bits must be decoded with low postponement.
ADVANTAGE :
? This is more efficient than using two separate SEC codes (one for the data bits and the other for the control bits) as this requires additional parity check bits.
? These flags are used to determine the processing of the data, and the associated control logic is commonly on the critical timing path.
? The clock frequencies used in current ASICs are typically in the range of 300 MHz to 1 GHz, and the clock frequencies in FPGAs are typically lower (under 400 MHz).
? To protect the control bits, the first three parity check bits can be assigned different values for each control bit, and the remaining parity check bits are not used to protect the control bits.
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