FIR Filter Design Based on FPGA
Abstract : The paper introduces structure characteristics and the basic principles of the finite impulse response (FIR) digital filter, and gives an efficient FIR filter design based on FPGA. Use MATLAB FDATool to determine filter coefficients, and designed a 16-order constant coefficient FIR filter by VHDL language, take use of QuartuslI to simulate filters, the results meet performance requirements.
? The application of parallel processing to an FIR filter involves the replication of the hardware units that exist in the original filter.
? The topology of the multiplier circuit also affects the resultant power consumption.
? They extensively use a modified common sub expression elimination algorithm to reduce the number of adders.
? A digital filter takes a digital input, gives a digital output, and consists of digital components.
? In a typical digital filtering application, software running on a DSP reads input samples from an A/D converter, performs the mathematical manipulations dictated by theory for the required filter type, and outputs the result via a D/A converter.
? To alleviate this problem, the main strategy is to make the slicing of LUT into desired number. It reduces the size of memory, with small increase in area requirement due to adders.
? Multiplier are costly in terms of area, many multiplier centric techniques are developed for implementation of FIR filter to resolve this issue.
? Research work found in two broad categories of FIR filter implementation, one by the use of multiplier, can categorized as Multipliered FIR filter and another, without use of multiplier as Multiplierless FIR filter.
? This paper presents, a hardware-efficient multiplierless FIR filter, implemented with distributed arithmetic.
• They have proposed a novel approach for a design method of a low power digital baseband processing.
• Thus proposed DA architecture enables FIR implementation with reduced area, mainly useful for, high order FIR filters.
• To evaluate the performance of the proposed scheme, 16 tap, symmetric lowpass FIR filter is implemented and synthesized.
• Area complexity and operating speed, on various number of LUT slices, of proposed circuit.
• In this research proposes a pipelined variable precision gating scheme to improve the power awareness of the system.
? VHDL can describe the same logic function in multiple levels, such as it can describe the structure of the circuit composition in the register level and describe the function and performance of the circuit in the behavior level.
? FIR filter coefficients can be got from the method of window function, the basic idea of window function is to have the narrowest main lobe width and side lobes as small as possible, so use Hamming window for the filter design.
? As the FIR system have a lot of good features, such as only zeros, the system stability, operation speed quickly, linear phase characteristics and design flexibility, so that FIR has been widely used in the digital audio, image processing, data transmission, biomedical and other areas.
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