A Closed Form Expression for Minimum Operating Voltage of CMOS D Flip Flop
Abstract : In this paper, a closed-form expression for estimating the minimum operating voltage (VDDmin) of D flip-flops (FFs) is proposed. VDDmin is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that VDDmin of FFs is a linear function of the square root of logarithm of the number of FFs, and its slope depends on the within-die variation of the threshold voltage (VTH) and its intercept depends on the balance between nMOS and pMOS, which is mainly due to the die-to-die VTH variation. The proposed expression of VDDmin is validated by the simulation results as well as the silicon measurements. Finally, we discuss the dependence of VDDmin on the device parameters.
? Existing analytical models for MOS devices are either too complex, thus obscuring the basic physical relations between voltages and currents, or they are inaccurate and discontinuous around the region of interest, i.e., near threshold.
? The models used in this paper are based on existing inversion charge models.
? Simple continuous models such exist but are purely empirical, so they lack the rigor and fitting-constant stability associated with the analytical model presented in this paper.
? The weak-inversion model is inaccurate at and above the device threshold voltage, which makes it difficult to perform analysis or establish trends for circuits operating near threshold.
? As power dissipation becomes the more serious problem, the more accurate estimation of the power dissipation is needed and in this context, studying PS is crucial for the future VLSI designs.
? In this paper, a closed-form expression is presented which resolves the above-mentioned problems and the future trend of the PS / (PD + PS) is discussed for the first time, which answers a long-standing question if the PS is getting more and more serious or not in the future.
? One more drawback is that the expressions include the solution of quadratic or cubic equations so that the expressions are complicated.
• The proposed technique shows that the clock slope condition can be undisturbed with deference to conventional assumptions.
• The proposed design of SET D flip flop shows better performance in terms of power dissipation and area among previous designs.
• The relative percentage power reduction in the proposed design is from 37 % to 52 % with respect to the previous designs.
• Due to advances in low power applications, low power digital CMOS has become more important, and the process technology has been advanced.
• In this paper, a SET D flip flop with 5 transistors is proposed.
? Energy efficient computing is becoming increasingly important in the Internet of Things era. The near/subthreshold operation is one of the most promising approaches to maximize the energy efficiency.
? Even with additional constraints (e.g., performance, reliability, yield), the energy-optimal operating point typically occurs near the threshold voltage.
? The EKV approximation is a useful and well-accepted model, so the corresponding maximum absolute error of 21% against can also be used as a validity bound for the other drain-current approximations.
? The model is first used to generate a closed-form analytical expression for delay, which is then used to give a closed-form equation for energy, and this is used to determine the minimum-energy operating point as a function of activity factor and frequency.
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