Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems
Abstract : Iterative methods are basic building blocks of communication systems and often represent a dominating part of the system, and therefore, they necessitate careful design and implementation for optimal performance. In this brief, we propose a novel field programmable gate arrays design of matrix–vector multiplier that can be used to efficiently implement widely adopted iterative methods. The proposed design exploits the sparse structure of the matrix as well as the fact that spreading code matrices have equal magnitude entries. Implementation details and timing analysis results are promising and are shown to satisfy most modern communication system requirements.
? Our aim is the elimination of the operation of calculating random values, in the state-of-the art section, we also discuss existing algorithms known as deterministic PSO (DPSO).
? In this paper we deal with digital implementation, it is more appropriate to take a closer look at existing solutions in digital technique.
? The modeling of the behavior of flocks of animals, e.g., ants or bees, it offers a good performance in problem solving tasks that require searching for a global optimum in situations where many local extrema exist.
? The way the agents change their locations is to some extent similar to how animals move in nature.
? In the communication context and more precisely in CDMA systems, which we will be considering in this brief, iterative methods have been used extensively in estimation and detection problems.
? To overcome this problem, pilot symbols (known symbols) are first sent to estimate the channel and then the channel estimate is used to recover (detect) the transmitted unknown data symbols.
? Hardware consumption is one of the main issues of iterative methods; thus, any practical design needs to scale gracefully as the number of users increases.
? Another issue to be concerned with is whether time requirement can still be met after increasing the number of users and the number of stages.
• In this work, we propose a novel metaheuristic algorithm that evolved from a conventional particle swarm optimization (PSO) algorithm for application in miniaturized devices and systems that require low energy consumption.
• Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection.
• Several efficient bit-parallel systolic multipliers using low hamming weight polynomials, such as trinomials and all-one polynomials (AOPs), have been proposed.
• The structure of the proposed trinomial-based multiplier, the multipliers for irreducible pentanomials can also be built with low-complexity systolic architectures.
? FPGAs are well suited for algorithms that exhibit high degrees of parallelism as the case with many iterative methods such as the Jacobi and conjugate gradient algorithms, which leads naturally to their efficient implementation on FPGAs.
? We specifically focus on the design of a matrix–vector multiplication that efficiently trades off between parallelism and delay.
? The proposed design balances between parallelism and delay to achieve efficient hardware consumption by exploiting sparsity of the multiplying matrix in the vector–matrix multiplication.
? Both estimation of the channel and detection of transmitted symbols lead to an optimization problem that can be solved efficiently using iterative methods.
|