A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
Abstract : This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of the proposed design is close to the existing maximum likelihood post-detection processing (ML-PDP) scheme, while resulting in a significantly lower complexity, i.e., and times fewer Euclidean distance (ED) calculations in the 16-QAM and 64-QAM schemes, respectively. The proposed design for the 16-QAM scheme is fabricated in a 0.13 CMOS technology and fully tested, achieving a 1.332 Gbps throughput, reporting the first fabricated design for SC-FDMA MIMO detectors to-date. A soft version of the proposed architecture is also introduced, which is customized for coded systems.
? LTE Advanced (LTE-A),which is an evolution of LTE, supports single-user spatial multiplexing of up to eight layers in the downlink and four layers in the uplink targeted to achieve peak data rates of 1 Gbps and 500 Mbps, respectively.
? However, the implementation of a MIMO detector in an SC-FDMA system is significantly more complicated than that of an OFDMA system.
? This is due to the fact that the transmitted data is mixed together because of the extra DFT block used naturally in an SC-FDMA system.
? Therefore, the implementation of a low-complexity MIMO detector is needed and is the main challenge in the SC-FDMA framework.
? Therefore, intelligent methods need to be devised to drastically reduce the complexity of the detection problem.
? A number of system-level solutions have been proposed to reduce the complexity of the MIMO detection problem in, however none of them have described a detailed hardware implementation.
? In the existing communication system, the interference coordination algorithms can only solve the single interference source problem.
? Though the data throughput rate is high, the complete parallel architecture is mainly controlled based on global wiring, therefore, the chip area is large, and problems of low clock frequency and high power consumption exist.
• In this paper, a detection scheme is proposed for MIMO SC-FDMA systems, which provides near-optimal performance with a significant reduction in the complexity especially for large constellation sizes.
• The proposed design is fabricated in a 0.13 CMOS technology and fully tested.
• Moreover, in order to benefit from the enhanced signal integrity offered by coded systems, the proposed hard decoding architecture is also modified to create optimized for area and the other, optimized for a better BER performance.
• The BER performance of the proposed detection scheme is close to ML-PDP while the reduction in the complexity is significant in large constellation sizes.
? The SC-FDMA utilizes a discrete Fourier transform-spread OFDM (DFT-S-OFDM) modulation with similar performance compared to the OFDM.
? Its main advantage is to provide a lower peak-to-average power ratio (PAPR), which makes it the technology of the choice for the uplink.
? The maximum likelihood (ML) receiver, on the other hand, offers an optimal bit error rate (BER) performance but incurs very high computational complexity especially in the SC-FDMA receivers.
? In this paper, a detection scheme is proposed for MIMO SC-FDMA systems, which provides near-optimal performance with a significant reduction in the complexity especially for large constellation sizes.
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