Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

Abstract : As the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use of power pins and power distribution networks for application/ observation of test data as well as delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, specifically the transmission of data through power lines. The main design objective of the proposed PLC receiver is the robust operation under variations and droops of the supply voltage rather than high data speed. The PLC receiver is designed and fabricated in CMOS 0.18-µm technology under a supply voltage of 1.8 V. The measurement results show that the receiver can tolerate a voltage drop of up to 0.423 V for a data rate of 10 Mb/s. The power dissipation of the receiver is 3.26 mW under 1.8 V supply, and the core area of the receiver is 74.9 µm × 72.2 µm.
 EXISTING SYSTEM :
 ? It is found that the power consumption of this new CMOS PLC receiver is only 1.228mW, which is too less than even half power of the presently existing design. ? Many challenges still exist such as, the need of proper provision for the thermally generated heat removal, the number of the input output pins that an IC needs, proper power supply injection etc., due to which there exists limits on incorporating functions inside ICs. ? Many variants of the same already exist, but a power efficient design is not yet met. ? This new work could reduce the power consumption to less than half of the presently existing CMOS PLC receiver and is found to be 1.228mWs.
 DISADVANTAGE :
 ? It is a general consensus among test engineers that accessibility, i.e., controllability and observability, to internal nodes for both 2-D and 3-D ICs is essential to address the testing problems. ? The problem is aggravated when a data signal travels through the power and ground planes of the package. ? One problem for the logic restorer is large peaks for logic 1 during a high clock period, which could damage the chip. ? The main problem was on the ability to withstand the noise level that is present in the test data which couples through the power lines.
 PROPOSED SYSTEM :
 • A robust receiver for PLC was proposed in ICs which employs the differential Schmitt trigger as the third stage of the receiver for better noise immunity and also to tolerate supply voltage variations and drops. • The signal extractor in the proposed power efficient design is a differential amplifier having diode connected loads. • In the proposed design, the resistive loads were replaced with diode connected transistors and the result of it was a further reduction in the power consumption of the receiver. • The proposed PLC receiver was designed and simulated in CMOS 0.18-µm technology with a supply voltage of 1.8 V.
 ADVANTAGE :
 ? The main advantage of using a differential Schmitt trigger is that, it is excellent in handling the situations of extreme noise and disturbances. ? The performance of the individual blocks of the PLC receiver was measured followed by the performance of the entire receiver. ? The traditional narrow-band communication systems, UWB signaling has several advantages, such as high data rate, low average power, and simple RF circuitry. ? The increase in system complexity is an advantage in the sense that the size of ICs can be reduced, with that there should be new inventions for proper data passage inside the same. ? The use of the same has another advantage that it reduces the noise levels that are already present in the signals.

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