New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata
Abstract : In this paper, we first theoretically re-defined output decimal carry in terms of majority gates and proposed a carry lookahead structure for calculating all the intermediate output carries. We have used this method for designing the multi-digit decimal adders. Theoretically, our best n-digit decimal adder design reduces the delay and area-delay product (ADP) by 50% compared with previous designs. We have implemented our designs using QCADesigner tool. The proposed QCADesigner based 8-digit PBA-BCD adder achieves over 38% less delay compared with the best existing designs.
? A unique approach to develop a QCA- based 32 bits BCD adder which can achieve higher computational speed than existing counterparts with occupying less area or count cell.
? The proposed work is focused on to develop a 32 bit BCD adder by adding two 32 bit BCD adder using Binary adders and if the sum is not valid BCD then we add 6 to the sum to get the valid BCD value.
? It has been proved that the proposed reversible BCD arithmetic circuit is higher than the existing logic in the literature; in phrases of some of rubbish outputs, constants inputs and the gate rely.
? Quantum-dot cellular automata (QCA) have been recognized as one of the technologies which could update field-impact transistor (FET)-based completely computing gadgets on the nano-scale diploma.
? The current silicon transistor technology faces challenging problems, such as high-power consumption and difficulties in feature size reduction.
? Nanotechnology is an alternative to these problems, and the international technology roadmap for semiconductors (ITRS) report summarizes several possible technology solutions.
• The proposed CFA-based BCD adder has the smallest area with the least number of cells.
• This research work proposes a modular design of a BCD adder in QCA and shows analyses based upon those designs A crucial building block for decimal operations is the decimal adder.
• The proposed BCD adder using majority gates is efficient in term of delay.
• The proposed shape is based totally on a today's algorithm that requires handiest 3 majority gates and two inverters for the QCA addition.
• It is mentioned that the bit-serial QCA adder makes use of a variation of the proposed one-bit QCA adder.
? These designs can be further optimized to reduce hardware complexity. Carry flow adder (CFA) based and carry lookahead adder (CLA) based BCD adders are presented in, which show good performance.
? Due to the proposed new formulations as presented in the previous sections, when the scale of the design increases, our proposed approach shows excellent performance in terms of delay.
? Moreover, exploits novel binary adder to propose the efficient 1-digit BCD adder, reducing comprehensive consumption.
? We have used different types of binary adders, such as RCA, CFA and parallel binary adder (PBA) for realizing the proposed multi-digit BCD adder.
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