A High speed and Power Efficient Voltage Level Shifter for Dual Supply Applications
ABSTARCT :
This brief presents a fast and power-efficient voltage levelshifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is due to the fact that not only the strength of the pull-up device is significantly reduced when the pull-down device is pulling down the output node, but the strength of the pull-down device is also increased using a low-power auxiliary circuit. Postlayout simulation results of the proposed circuit in a 0.18-µm technology demonstrate a total energy per transition of 157 fJ, a static power dissipation of 0.3 nW, and a propagation delay of 30 ns for input frequency of 1 MHz, low supply voltage level of VDDL = 0.4 V, and high supply voltage level of VDDH = 1.8 V.
EXISTING SYSTEM :
? One of the most effective ways to reduce dynamic and short-circuit power consumption of digital circuits is lowering the value of the power supply voltage.
? On the other hand, reducing the supply voltage increases the propagation delay of the circuits. Moreover, less headroom in analog circuits decreases signal swings and therefore increases the sensitivity to noise.
? When the voltage difference between VDDL and VDDH is high and particularly when the input voltage is in subthreshold range, this circuit will no longer be able to convert the voltage levels.
? This is because the currents of the pull-down transistors are smaller than those of the pull-up devices.
DISADVANTAGE :
? In order to avoid these problems dual supply architecture are introduced in which a low voltage (VddL) is supplied for the blocks on the noncritical paths while a high supply voltage (VddH) is applied to the analog and the highspeed digital blocks.
? We propose to incorporate the current limiting diode-connected transistor with a crosscoupled transistor structure to minimize the current contention problem while achieving a very small input voltage.
? To overcome this problem, we improve the split-control output buffer to support a wider output voltage range while minimizing the static current and reducing the propagation delay.
PROPOSED SYSTEM :
• Several level shifter (LS) circuits were recently proposed to allow voltage conversion from the deep subthreshold regime up to the nominal supply voltage level.
• In a system with dual supply voltages, level-shifting circuits are needed to convert the lower logic levels into the higher ones to provide correct voltage levels for the next digital blocks.
• In order to alleviate the degradation of the overall performance of the circuit, the required level shifters must be designed with minimum propagation delay, power consumption, and silicon area.
• In order to have more power saving in the low-supply blocks, the employed level shifters must be able to convert the extremely low values of VDDL to even lower than the threshold voltage of the input transistors.
ADVANTAGE :
? In order to alleviate the degradation of the overall performance of the circuit, the required level shifters must be designed with minimum propagation delay, power consumption, and silicon area.
? In order to investigate the benefits of technology scaling on the performance, all the circuits have been optimally designed and simulated in a standard TSMC 90-nm CMOS technology as well.
? A fast and power-efficient voltage level shifter is proposed, which is able to convert extremely low values of the input voltages.
? In order to decrease the static power consumption, a dynamic current generator, which turns on only during the transition times, can be used.
? In order to have a better comparison between the structures, the well-known PDP can be used as a figure of merit.
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