Designing Tunable Sub-threshold Logic Circuits Using Adaptive Feedback Equalization
Abstract : Ultralow-power subthreshold logic circuits are becoming prominent in embedded applications with limited energy budgets. Minimum energy consumption of digital logic circuits can be obtained by operating in the subthreshold regime. However, in this regime process variations can result in up to an order of magnitude variations in ION/IOFF ratios leading to timing errors, which can have a destructive effect on the functionality of the subthreshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption are required. In this paper, we propose a tunable adaptive feedback equalizer circuit that can be used with a sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in the subthreshold digital logic circuits. We also present detailed energy-performance models of the adaptive feedback equalizer circuit. As part of the modeling approach, we also develop an analytical methodology to estimate the equivalent resistance of MOSFET devices in subthreshold regime. For a 64-bit adder designed in 130 nm, our proposed approach can reduce the normalized variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage.
? In Existing system propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance–capacitance (RC) delay in interconnects.
? The existing equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus.
? This means that the data enters into the flip-flop at leading/trailing edge of the clock pulse while it is obtained at the output pins during trailing/leading edge of the clock pulse.
? This conventional master slave positive edge triggered flip flop which has the more transistor.
? To avoid the metastability problem in the E-flip-flop, both the setup time and hold time constraints should be satisfied.
? This in turn has a significant impact on the drive current due to the exponential relationship between the drive current and the threshold voltage of the transistors in the subthreshold regime.
? Body-biasing has also been proposed to mitigate the impact of variations.
? The sampling of a glitch leads to the marginal increase in the dynamic energy of the sequential logic block (0.72% increase in the 64-bit adder), but it has a negligible impact on the overall energy consumption as it is not the dominant energy component in the subthreshold regime.
• We propose using an adaptive feedback equalizer circuit in the design of tunable sub threshold digital logic circuits.
• The use of gates of different drive strengths has also been proposed to overcome process variations.
• This proposed method has designed with original nonqualified design; equalized design with one feed back ON buffer inserted no equalized design.
• The proposed application of tunable adaptive feedback equalizer circuit used to reduce the normalized variation of total delay along the critical path and the dominant leakage energy of the digital CMOS logic operating in the sub threshold regime.
? The use of subthreshold digital CMOS logic circuits is becoming increasingly popular in energy-constrained applications where high performance is not required.
? This adaptive feedback equalizer circuit can reduce energy consumption and improve performance of the subthreshold digital logic circuits.
? We present detailed analytical models (AMs) for performance and energy of the adaptive feedback equalizer circuit.
? These models can be easily used in combination with the existing performance and energy models for subthreshold circuits to generate subthreshold designs that meet energy and/or performance constraints.
|