Obfuscating DSP Circuits via High-Level Transformations
Abstract : This paper presents a novel approach to design obfuscated circuits for digital signal processing (DSP) applications using high-level transformations, a key-based obfuscating finite-state machine (FSM), and a reconfigurator. The goal is to design DSP circuits that are harder to reverse engineer. Highlevel transformations of iterative data-flow graphs have been exploited for area-speed-power tradeoffs. This is the first attempt to develop a design flow to apply high-level transformations that not only meet these tradeoffs but also simultaneously obfuscate the architectures both structurally and functionally. Several modes of operations are introduced for obfuscation where the outputs are meaningful from a signal processing point of view, but are functionally incorrect. Examples of such modes include a third-order digital filter that can also implement a sixth-order or ninth-order filter in a time-multiplexed manner. The latter two modes are meaningful but represent functionally incorrect modes. Multiple meaningful modes can be exploited to reconfigure the filter order for different applications. Other modes may correspond to nonmeaningful modes. A correct key input to an FSM activates a reconfigurator. The configure data controls various modes of the circuit operation. Functional obfuscation is accomplished by requiring use of the correct initialization key, and configure data. Wrong initialization key fails to enable the reconfigurator, and a wrong configure data activates either a meaningful but nonfunctional or nonmeaningful mode. Probability of activating the correct mode is significantly reduced leading to an obfuscated DSP circuit. Structural obfuscation is also achieved by the proposed methodology via high-level transformations. Experimental results show that the overhead of the proposed methodology is small, while a strong obfuscation is attained. For example, the area overhead for a (3l)th-order IIR filter benchmark is only 17.7% with a 128-bit configuration key, where 1 = l = 8, i.e., the order of this filter should be a multiple of 3, and can vary from 3 to 24.
? In this work, the watermark bits were added intothe outputs of the existing and free transitions of STG.
? As this paper is the first attempt to develop a methodology to obfuscate DSP circuits by utilizing high-level transformations, it is hard to compare with other existing obfuscation methods which are general to a wide variety of designs.
? Therefore, we have introduced two metricsto analyze the security, Most of the hardware obfuscation techniques in this paper can also be applied to DSP circuits.
? However, the use of high-level transformations from a security perspective has not been incorporated into any of these prior hardware obfuscation techniques.
? The challenge of this problem is how to generate meaningful variation modes from a signal processing point of view such that the DSP circuit can also be operated in a reconfigurable manner.
? Among all the hardware security problems, piracy islikely to be the most ubiquitous and expensive one.
? The transient sensitivity of nonlinear circuits is a challenging problem as itmay require substantial amount of storage and CPU time alsoon modern computers.
? The active participation of external entities inthe design and manufacturing flow has produced numerous hardware security issues.
• A variety of techniques has been proposed for fighting against hardware piracy.
• A number of hardware obfuscation schemes have been proposed that modify the finite-state machine (FSM)representations to obfuscate the circuits.
• In addition, meaningfulvariation modes enable our proposed design methodology to be adaptable to reconfigurable applications.
• A secure reconfigurable switch design is incorporated into the proposed design scheme to improve the security.
• In the proposed obfuscation methodology, the variation modes and the additional obfuscating circuits could also be designed systematically based on the high-level transformations.
? These techniques can be applied at the algorithm or the architecture level to achieve a tradeoff among different metrics of performance, such as area, speed, and power.
? The choice of folding set is critical to the performance of the folded structure, since an appropriate choice of folding order can lead to an architecture with lower area and power.
? There can be a degradation of the performance with respect to latency if null operations are inserted into the obfuscated design.
? The main advantage of the proposed methodology is the generation of meaningful variation modes from a signal processing point of view, since the meaningful modes create ambiguity to the adversary such that it is hard for the adversary to distinguish the desired functionality from other variation modes.
|