Low Power Split Radix FFT Processors using Radix-2 Butterfly Units

Abstract : Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT is the same as radix-2 FFT, and therefore, the conventional address generation schemes of FFT data could also be applied to SRFFT. However, SRFFT has irregular locations of twiddle factors and forbids the application of radix-2 address generation methods. This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power at the expense of using more hardware resources. In addition, two novel address generation algorithms for both the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the conventional radix-2 shared-memory implementations, the proposed design achieves over 20% lower power consumption when computing a 1024-point complex-valued transform.
 EXISTING SYSTEM :
 ? A highly efficient FFT memory addressing scheme with significant logic reduction and delay improvements compared to existing shared-memory based FFT methods. ? A pipelined architecture provides high throughputs, but it requires more hardware resources at the same time. ? One or multiple pipelines are often implemented, each consisting of butterfly units and control logic. ? In contrast, the sharedmemory-based architecture requires the least amount of hardware resources at the expense of slower throughput.
 DISADVANTAGE :
 ? Power consumption is an important issue in modern high frequency and low power designs. ? Although a software solution for the indexing problem has been given in, the indexing scheme is designed for the L butterfly structure, which is not suitable for the hardware implementation due to its uneven latencies. ? Some previous works such as use lookup tables to solve the indexing problem. ? It is obvious that the proposed algorithm requires significantly less memory than the lookup table approach.
 PROPOSED SYSTEM :
 • The proposed architecture enables power reduction in two ways , it achieves multiplicative complexity then radix-4 algorithm while using a shorter datapath reduces glitch power and the complex multipliers can be gated to saves dynamic power. • The proposed architectures are not only multiplierless and achieve unity gain, but also require the smallest number of adders among current SDF FFTs. • The FFT can be implemented in 256 points FFT processor with efficient algorithm and technique to improve the efficiency of the proposed system.
 ADVANTAGE :
 ? In the shared-memory architecture, an efficient addressing scheme for FFT data as well as coefficients (called twiddle factors) is required. ? At each clock cycle, two FFT data are provided by memory banks and one butterfly unit is used to process the data. ? Those multiplications involving Wn are called nontrivial multiplications, because complex multipliers are used to complete these operations. ? The limitation of the proposed design is the large resources used in the butterfly unit. ? A large number of cells are used to implement the memory banks, which become the most power hungry component in the design.

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