Pre-Encoded Multipliers Based on Non-Redundant Radix-4Signed-Digit Encoding
Abstract : In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {-1, 0, +1, +2} or {-2, -1, 0, +1}, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.
? Due to the existence of an error-correcting word (ECW) generated by MBE and RB encoding, the RB multiplier generates an additional RB partial product rows.
? When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content.
? Signed-digit decimal adders have the benefit of carry-free addition although a carry-propagate adder must be used to transform the signed-digit sum into an unsigned sum.
? A constant addition technique will be applied to both the correction step in signed-digit decimal addition and conversion to binary- coded decimal (BCD).
? The hard multiples problem in RB multiplier can be resolved by difference of two simple power-of-two multiples.
? This work presents a new radix-16 RB Booth Encoding (RBBE-4) to avoid the hard multiple of high-radix Booth encoding without incurring any ECW.
? One of the many solutions of realizing high speed multipliers is enhancing parallelism which helps in decreasing the number of subsequent calculation levels.
? The number of add-subtract operations and shift operations become variable and causes inconvenience in designing parallel multipliers.
• In, a CSD-based programmable multiplier setup was proposed for social occasions of pre-chosen coefficients that offer certain features.
• We propose encoding these coefficients in the Non-Redundant radix-4 Signed-Digit (NR4SD) outline.
• The proposed pre encoded NR4SD multiplier designs are more area and power capable stood out from the normal and pre-encoded MB plots.
• The proposed method leads to make high-speed and low-power RB multipliers.
• The proposed RBBE-4 multiplier achieves significant improvement in delay and power consumption compared with the RB MBE multiplier and the current reported best RBBE-4 multipliers.
? The multiplier is a basic component for implementing computationally intensive applications, its architecture seriously affects their performance.
? The performance of the proposed designs is considered with respect to the width of the input numbers, i.e., 16, 24 and 32 bits.
? We observe that the pre-encoded NR4SD architectures are more area efficient than the conventional or pre-encoded MB designs with respect to their performance in the lowest possible clock periods.
? The size of ROM used to store the groups of coefficients is significantly reduced as well as the area and power consumption of the circuit.
? However, this multiplier design lacks flexibility since the partial products generation unit is designed specifically for a group of coefficients and cannot be reused for another group.
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