Temporarily Fine Grained Sleep Technique for Near and Subthreshold Parallel Architectures
Abstract : This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is to suppress leakage energy dissipation of the idle portions of circuits during active modes, which can allow us to wholly transform the throughput improvement from parallel architectures into energy savings via deep voltage scaling. We begin by investigating the efficacy of parallel and pipeline architectures in the near- and subthreshold circuits. The investigation reveals that active energy dissipation largely undermines the ability of deep voltage scaling to transform excessive throughput into energy savings. Techniques, such as power-gating switches (PGSs), can mitigate active-leakage power dissipation; however, the overhead for entering and exiting sleep modes can offset the energy savings provided by sleep mode, particularly if sleep time is fine grained for suppressing active leakage. Therefore, in this paper, we propose a PGS design technique, inspired by the so-called zigzag supercutoff CMOS, in order to optimize the overheads of mode transitions of PGS in near- and subthreshold circuits. The proposed technique enables to have circuits in sleep mode for as short as a single clock cycle with a negligible amount of energy and delay overheads. We apply our proposed design to parallel multiplier-based test circuits operating at near- and subthreshold voltages. Simulations show a significant improvement in energyefficiency over baselines at the same throughput.
? There exists a fundamental limit for energy savings from voltage scaling in the subthreshold regime regardless of Vth.
? There also exists an optimal pipeline depth for maximum performance in purely performance-constrained systems.
? However, even the modified R4MDC architecture consumes 52% of its total energy in memory, indicating that further room for improvement exists in memory utilization.
? The proposed design improves performance by 2 through parallelism while consuming only 35% of its total energy in memory, indicating a greater degree of voltage scalability and potential improvements.
? The gate-leakage problem, however, is negligible at nearand subthreshold, because gate leakage is exponentially small at lower VDDs, making the ZSCCMOS technique much more desirable.
? The existing works on parallel and pipelined architectures, however, have emphasis on nominal VDD designs, having little or no attention on a crucial issue that has greater significance in near- and subthreshold circuits: active-leakage dissipation.
? We study the impact of circuit utilization and the scalability of parallel architectures.
? Hardware utilization has a strong impact on the efficacy of parallel architectures to trade off throughput for energy savings via voltage scaling.
• This paper proposes a design approach targeting circuits operating at extremely low supply voltages, with the goal of reducing the voltage at which energy is minimized, thereby improving the achievable energy efficiency of the circuit.
• The proposed methods accomplish this by minimizing the circuit’s ratio of leakage to active current.
• A parallel-pipelined FFT architecture is then proposed to maximize computational element and memory utilization, while reducing memory size and overall leakage energy.
• In, a power-aware pipeline strategy is proposed and the power–performance trade-off is demonstrated.
? As power and energy have come to be of greater significance, designers have had to conscientiously devise techniques that aim greater energy-efficiency while avoiding or mitigating performance degradation.
? We can employ parallel and pipeline architectures, and by scaling VDD, it is possible to trade off throughput improvements from those architectural techniques for higher energy-efficiency.
? Active-leakage energy dissipation, consequently, becomes critical to runtime computing energyefficiency.
? In order to improve computing energy-efficiency beyond the conventional limit, i.e., VOPT, it is of great importance to reduce leakage energy dissipation during active modes.
|