Radiation Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Applications
ABSTARCT :
In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event upset as well as single-event–multiple-node upsets due to the charge sharing among OFF-transistors. Moreover, the HSPICE simulation results show that the write speed and power consumption of the proposed RSP-14T are improved by ~65% and ~50%, respectively, compared with those of the radiation hardened design (RHD)-12T memory cell.
EXISTING SYSTEM :
? In the radiation environment, when the heavy ion is incident on the semiconductor material, the particles will be ionized. These excess charges will be collected by the sensitive nodes of the device.
? The charge sharing results in single-event–multiple-node upsets (SEMNUs), which is becoming the main effect of energetic particle strikes in emerging nanometer CMOS technology.
? The soft error rate (SER) in SRAM is increased with the technology scaled in the nanometer regime. In order to reduce the SER, numerous alternatives have been proposed to the standard 6T SRAM cell.
? The main reinforcement method is through constructing special topology of transistor connections inside cells to achieve circuit-level protection.
DISADVANTAGE :
? During the write operation, the feedback mechanism will be interrupted easily.
? The charge sharing between transistors will be neglected.
? To reduce the impact of charge sharing on N2 and N0 when P2 is hit by a particle, they are also moved away from P2.
? Low-Power and High-Performance have become a burning issue in VLSI industries these days.
PROPOSED SYSTEM :
• In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness.
• The proposed radiation-hardened bitcell is a pioneer solution for embedded memories in low-power space applications.
• Various bitcell designs and architectural techniques have been proposed to enable operation deep into the subthreshold region.
• The proposed bitcell is specifically designed to enable robust, low-voltage, ULP operation in space applications and other high-radiation environments.
• The proposed 13T bitcell features single-ended readout through the read access transistor (N8).
ADVANTAGE :
? During the write operation, the feedback mechanism will not be interrupted easily.
? Requires low area.
? Due to their static power consumption, scaling the supply voltage of the SRAM macros is an efficient method to reduce total chip power.
? The SET is obtained by heavy ions striking on drain of OFF-transistors, and the efficiency of the charge sharing among the OFF-transistors is evaluated by the angle of the hit.
? The most efficient way to achieve ULP operation in integrated circuits is to aggressively reduce the supply voltage (VDD) and operate all components of the chip in the near-threshold or subthreshold region, thereby significantly reducing both static and dynamic power consumption.
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