Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
Abstract : The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (VDD), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full VDD, without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology.
? In this paper, a study of the existing SRAM (Static Random Access Memory) cell topologies using various FET (Field Effect Transistor) low power devices has been done.
? High-k dielectric materials and thinner gate oxides can be used to palliate the issue by further elevating the capacitance that exists between channel and region.
? There by new technologies are taking birth and the existing ones are being further developed.
? The proposed 10T SRAM exhibits reduction in leakage power when compared with existing single ended 10T SRAM.
? A comparative analysis is done with some existing SRAM topologies in terms of energy and area.
? The widespread use of battery powered applications, such as handheld smart devices and implantable medical devices, low-power operation has become a critical issue associated with the system-on-chip (SoC) design.
? The aforementioned alternatives do not address the half-select issue without a write-back scheme.
? To address the half-select issue without the write-back scheme, a 10T SRAM cell exhibiting a cross-point structure was proposed.
? To address this disadvantage, an average-8T SRAM architecture based on a 130-nm technology was proposed; this SRAM architecture is a good alternative to the previously proposed SRAMs in that it addresses the half-select issue with no write-back scheme, and it exhibits a competitive area.
• In the proposed architecture scheme of full swing is determined by cross coupled PMOSs and the gate of the read buffer is driven by full Vdd without the use of boosted word line voltage.
• So proposed SRAM cell is added with a decoupled read port that avoids this trade off to which bit inter leaving is not applied.
• To address this issue without using write back scheme 10T SRAM cell of cross point structure was proposed.
• The switch and cross coupled pMOSs of the proposed SRAM are the difference from average 8T SRAM architecture.
• This proposed buried powered SRAM is best for high performance, high density and low power memory systems in advanced processors.
? The advantage of adding a decoupled read port is that it eliminates the tradeoff between the read stability and the write ability in the SRAM array to which the bit-interleaving is not applied; thus, the read stability and write ability can be optimized separately, facilitating a low-voltage operation.
? The advantage of the proposed SRAM architecture is that it eliminates the tradeoff between the read stability and the read delay.
? In this regard, the advantage of the proposed SRAM is that it eliminates the unnecessary RBL discharge by using a buffer foot that is forced to high during the write operation.
? An advantage of the average-8T SRAM architecture is that it does not require a write-back scheme for bit-interleaving, and it exhibits a competitive area.
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