Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
Abstract : In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, singleoutput, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.
? There exists a proper subset of uniting Boolean functions, called threshold functions, which can be fundamentally computed by different mechanisms, which presents the possibility of further improvements in power consumption, performance, and area, which has not been sufficiently explored.
? Energy consumption of proposed flip-flop is compared with an existing leakage optimized CMOS flip-flop to obtain an optimum inactive period duration.
? There exist several ways to implement scan for a p NAND cell has negligible impact’s on the cell’s performance and robustness during normal operation.
? An efficient solution to the problem of computing the g functions is presented, given a unate function F and a threshold function H.
? The TLL does not consider the problem of coupling noise in the presence of floating nodes.
? In contrast, the scan mechanism of a pNAND is completely nonintrusive and has minimal impact on its robustness and delay.
? While these gates functioned well, their main drawbacks were large delay, area, dc power dissipation, and the requirement of precise capacitance values.
? Although the variant B-CTL eliminated the need for precise capacitance values by comparing relative voltages, it still retained the other drawbacks.
• We propose a new approach, thus providing a new choice to low leakage power VLSI designers.
• The main of the SAFF proposed in and is the slave element, composed by a set/reset (SR) NAND latch.
• To improve the robustness to parametric variability, advanced device or circuit architectures such as dual-Vth TFT logic, pseudo CMOS logic, differential logic and positive- feedback level shifter logic were proposed.
• The proposed non volatile flip-flop design in detail along with transient simulations performed using the compact model to demonstrate functionality, energy consumption and data restore operation reliability for a range of voltage supply levels.
? It may be possible to switch to a cheaper and more efficient voltage regulator for hybrid circuits.
? The focus has shifted to the higher levels of design, including power-efficient micro architectures, memory, compilers, and OS, and system level control, including thermal-aware dynamic frequency and voltage control, thread migration among processor cores, and so on.
? Such implementations offer nothing new, and in fact, can be quite inefficient for implementing large fan-in threshold functions in terms of speed, power, and area.
? The use of TLGs in conventional ASIC design has not been thoroughly explored due to the lack of efficient and reliable gate implementations and the infrastructure required for automated synthesis and physical design.
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