High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
ABSTARCT :
In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.
EXISTING SYSTEM :
? In the existing system the multiplier is used which consumes more power. Instead of using this structure that consists of AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) is used for skip logic.
? The existing CSKA has more delay and power consumption and some of the proposed methodologies uses some complex methodologies to achieve less delay and low power consumption.
? This originates from the fact that, in the Conv-CSKA, the skip logic (AOI or OAI compound gates) is not able to bypass the zero carry input until the zero carry input propagates from the corresponding RCA block.
DISADVANTAGE :
? This problem, in the proposed structure, we have used an RCA block with a carry input of zero (using the concatenation approach).
? An adjustment of the structure, based on the variable latency technique, which in turn lowers the power consumption without considerably impacting the CSKA speed, is also presented.
? The impact of voltage scaling on the efficiency of the proposed CSKA structure (from the nominal supply voltage to the near-threshold voltage).
? The CSKA configuration (i.e., the number of the FAs per stage) has a great impact on the speed of this type of adder.
PROPOSED SYSTEM :
• In this paper, a static CMOS CSKA structure called CI-CSKA was proposed, which displays a higher speed and lower energy utilization compared with those of the conventional one.
• The efficiency of the proposed structure for both FSS and VSS was studied by comparing its power and delay with those of the Conv-CSKA, RCA, CIA, SQRT-CSLA, and KSA structures.
• The hybrid variable latency augmentation of the proposed structure which brings down the power utilization without impressively affecting the speed is displayed.
• In this paper proposed as a review to improve the efficiency power carry skip adder.
ADVANTAGE :
? The dependence of the power (and performance) on the supply voltage has been the motivation for design of circuits with the feature of dynamic voltage and frequency scaling.
? There are different types of the parallel prefix algorithms that lead to different PPA structures with different performances.
? The performance of the proposed hybrid variable latency CSKA structure is compared with those of some other variable latency adders, including RCA, C2SLA, and hybrid C2SLA.
? A design strategy for constructing an efficient CSKA structure based on analytically expressions presented for the critical path delay.
? In, the efficiency of this method for reducing the power consumption of the RCA structure has been demonstrated.
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