Implementation of Sub-threshold Adiabatic Logic for Ultralow-Power Application
Abstract : Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralowpower circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.
? A CMOS transistor (or device) has four terminals: gate, source, drain, and a fourth terminal that we shall ignore until the next section. A CMOS transistor is a switch.
? The switch must be conducting or on to allow current to flow between the source and drain terminals (using open and closed for switches is confusing-for the same reason we say a tap is on and not that it is closed).
? The transistor source and drain terminals are equivalent as far as digital signals are concernedwe do not worry about labeling an electrical switch with two terminals.
? Multiplier is an important building block in applications such as digital signal processing, communication systems and arithmetic logic units.
? The design of SAL requires a deep knowledge of the main features of the adopted logic style, such as power dissipation, leakage current, impact of temperature variation, operating frequency, and noise immunity.
? In particular, the impact of temperature variation on leakage dissipation, output swing, etc., has been discussed thoroughly in this paper.
? Complex architecture and clock synchronization are the major drawbacks of full adiabatic logic circuits. Threshold voltage of the transistors in sub-threshold based digital circuits is higher than the supply voltage.
• In adiabatic logic circuits, ramp type supply voltage is used to slow down the charge transport mechanism. Hence, the supply clock plays the pivotal role.
• A ramp type supply voltage f(t) is considered, which gradually swings in between logic 0 (Gnd potential) and logic 1 (VDD) in time duration 2T, where f (=1/2T ) is the supply clock’s frequency.
• The power supply waveform f(t) can be divided into charging phase, when f(t) ramps up from 0 to VDD in 0 to T unit time and discharging phase when f(t) ramps down from VDD to 0 in T to 2T unit time.
• The proposed adiabatic logic circuit is advantageous for the design of ultralow-power digital circuits.
? These emerging applications have low energy as the primary concern instead of performance, with the eventual goal of harvesting energy from the environment.
? The performance requirements are quite relaxed in many of these energy efficient subthreshold applications, we believe that the adiabatic style can be used efficaciously in a subthreshold regime to make the circuit more energy efficient.
? As SAL is efficacious where instead of performance, power dissipation is major concern. For example, in implanted biomedical systems, the circuits remain active for a very small span of time and remain idle for most of the time.
? Therefore, the SAL-based CLA is also area efficient in comparison with the conventional structure.
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