Efficient Design for Fixed Width Adder-Tree
ABSTARCT :
Conventionally, fixed-width adder-tree (AT) design is obtained from the full-width AT design by employing direct or post-truncation. In direct-truncation, one lower order bit of each adder output of full-width AT is post-truncated, and in case of post-truncation, {p} lower order-bits of final-stage adder output are truncated, where p = dlog2 Ne and N is the input-vector size. Both these methods does not provide an efficient design. In this paper, a novel scheme is presented to obtain fixed-width AT design using truncated input. A bias estimation formula based on probabilistic approach is presented to compensate the truncation error. The proposed fixed-width AT design for input-vector sizes 8 and 16 offers (37%, 23%, 22%) and (51%, 30%, 27%) areadelay product (ADP) saving for word-length sizes (8, 12, 16), respectively, and calculates the output almost with the same accuracy as the post-truncated fixed-width AT which has the highest accuracy among the existing fixed-width AT. Further, we observed that Walsh-Hadamard transform based on the proposed fixed-width AT design reconstruct higher-texture images with higher peak signal to noise ratio (PSNR) and moderate-texture images with almost the same PSNR compared to those obtained using the existing AT designs. Besides, the proposed design creates an additional advantage to optimize other blocks appear at the upstream of the AT in a complex design.
EXISTING SYSTEM :
? Parallel multipliers are fundamental building blocks in multimedia and digital many applications, the inputs and the output of the multiplier have the same bit width.
? These circuits are denoted in literature as fixed-width multipliers or fixed width multipliers.
? The most obvious way to design a fixed-width multiplier uses a full-width multiplier, whose output is fixed width/rounded to n bits by n discharging the less-significant bits of the products.
? The fixed-width property, however, can be exploited to simplify the multiplier structure, with the aim of improving power and speed.
? Better accuracy is obtained in the so-called variable-correction (or adaptive) fixed-width multipliers.
DISADVANTAGE :
? Word-length growth is a common problem encountered when multiplication and addition are performed in fixed-point arithmetic.
? The optimized AT of is specific to MCM based design and none of the existing design discusses the issues related to fixed-width implementation of AT.
? This method cannot reduce noises which are added to the input signals. If the inputs are supplied with errors, then these errors will also reflect in the output.
? To further lower the compensation error, also consider the impact of truncated products with the second most significant bits on the error compensation.
PROPOSED SYSTEM :
• A high accuracy linear compensation method for fixed width booth multiplier is proposed.
• To propose linear compensation method is applied to the fixed-width Booth multiplier which reduces number of partial product generation which reduces delay of the partial product generation.
• The proposed linear compensation method provides a flexible and high accuracy to fixed-width Booth multipliers.
• we propose a parallel fixed-width multiplier design that receive two n-bit numbers and produce a n bit product.
• To design the proposed fixed-width multiplier, three multiplication modules are used that can work as independent smaller-precision multiplications.
ADVANTAGE :
? Low-power, area-efficient and high-performance computing systems are increasingly used in portable and mobile devices.
? It is necessary to study the error performance of fixed width AT designs along with their hardware and time complexities.
? The existing FX-AT-PT design does not have this feature and its performance entirely depends on the magnitude of post-truncation error irrespective of pixel variation of input vector.
? An efficient FL-AT design is proposed in using the approximate adder of for imprecise realization of Gaussian filter for image processing applications.
? It is observed that direct truncation and post-truncation methods does not provide an efficient FX-AT design.
|