ENERGY EFFICIENT FAST CARRY SELECT ADDER
ABSTARCT :
To reduce the power and time delay of the adder. Power consumption and performance are critical parameters in the design of digital circuit in general. In the case of digital processing systems (especially the portable ones), owing to limited power budgets and reliability concerns, achieving a desired performance level can be challenging. Adders are key building blocks in arithmetic and logic units (ALUs). Adders, which are utilized to perform other operations such as subtraction, multiplication, and division are among the most power hungry components in processors and are often hot-spot locations . Minimizing the delay and power consumption of these blocks is an important, yet challenging, undertaking.
EXISTING SYSTEM :
A conventional carry select adder (CSLA) is an RCA–RCA configuration that generates a pair of sum words and output carry bits corresponding the anticipated input-carry (cin = 0 and 1) and selects one out of each pair for final-sum and final-output-carry. A conventional CSLA has less CPD than an RCA, but the design is not attractive since it uses a dual RCA. Few attempts have been made to avoid dual use of RCA in CSLA design. Kim and Kim used one RCA and one add-one circuit instead of two RCAs, where the add-onecircuit is implemented using a multiplexer (MUX). In a SQRT CSLA, CSLAs with increasing size are connected in a cascading structure. The main objective of SQRT-CSLA design is to provide a parallel path for carry propagation that helps to reduce the overall adder delay.two sets of 2-bit RCAs.
DISADVANTAGE :
• The existing RCA system is to consume more power and area.
• To consume more time for carry generation process.
• To affect the overall adder architecture performance level.
PROPOSED SYSTEM :
In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA.In the proposed scheme, the CS operation is scheduled before the calculation of final-sum, which is different from the conventional approach.
ADVANTAGE :
The output from the mux adds up a delay of 3 which makes C3 (t=13), Sum3 (t=12), Sum2 (t=10), this delay is caused because of the operation time required by the mux. Where the C3 is given as the carry input to the next multiplexer to start functioning.
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