VEDIC MULTIPLIER USING HALF ADDER AND FULL ADDER FOR MODERN PROCESSORS

Abstract : Research is conducted in VLSI circuits and computer-aided design, building blocks for new circuit technology, integrated circuit testing and fault diagnosis, digital signal processing, computer-aided synthesis, field programmable gate arrays (FPGAs), and design of low-power circuits. Software tools are under development to assist engineers in the simulation and design of VLSI circuits. Portable communication and computation have driven the need for low-power electronics. Recent progress has been made in creating tools for estimating power dissipation in CMOS circuits. The research approach is to use accurate and efficient power estimation techniques to drive the design of new low-power systems. Software tools for testing integrated circuits, rapid fault simulation, and failure analysis are also being developed.

 EXISTING SYSTEM :

 An array multiplier is very regular in structure. It uses short wires that go from one full adder to adjacent full adders horizontally, vertically or diagonally [3]. An n × n array of AND gates can compute all the terms simultaneously. The terms are summed by an array of “n [n - 2]”full adders and „n? half adders. The shifting of partial products for their proper alignment is performed by simple routing and does not require any logic. The number of rows in array multiplier denotes length of the multiplier and width of each row denotes width of multiplicand. The output of each row of adders acts as input to the next row of adders. Each row of full adders or 3:2 compressors adds a partial product to the partial sum, generating a new partial sum and a sequence of carries.

 DISADVANTAGE :

 The main disadvantage of the array multiplier is the worst-case delay of the multiplier proportional to the width of the multiplier. The speed will be slow for a very wide multiplier.

 PROPOSED SYSTEM :

 In this proposed system, reduced the number of logic levels, thus reducing the logic delay. This proposed multiplier is based on Vedic mathematic. There are two sutras are used for multiplication. • Nikhilam Navatascaramam Dastah • Urdhvya Triyakbhyam.

 ADVANTAGE :

 Proposed system includes Urdhvya Triyakbhyam. The multiplier is based on an algorithm Urdhva Tiryagbhyam (Vertical and crosswise). These sutras show how to handle multiplication of larger number (N X N bits) by breaking it into smaller sizes. For multiplier, first the basic blocks, that 2x2 multiplier are made and then, 4x4 block, 8x8 block, 16x16 block and 32x32 have been made to design a 64x64 multiplier.