A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing
Abstract : This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to come at a near-zero energy cost. Both an instruction accurate (IA) and a cycle accurate (CA) model of the new architecture are used to evaluate six IoT baseband processing test benches including FSK demodulation and LoRa preamble detection. Simulation results show cycle count improvements from 19% to 68%. Post synthesis simulations for a target 22nm FD-SOI technology show less than 1% power and 28% area overheads, respectively, relative to a baseline RV32IM design. Power simulations show a peak power consumption of 380 W for Bluetooth LE demodulation and 225 W for LoRa preamble detection (BW = 500 kHz, SF = 11).
? The greater than comparison is done using the existing comparator, and the less than comparison is done in parallel by the adder.
? When different CPUs co-exist, they can either run the same ISA with a different micro architecture, or implement different ISA extensions of the main one.
? As signal theory algorithms are often based on frequency-domain transformations built on complex domains, having hardware support for complex arithmetic increases performance when executing such algorithms.
? Leveraging the existing hardware infrastructure for the pSIMD support, complex instructions between 16 bit data can be added with negligible overhead.
? Single-issue in-order cores with a high IPC are typically more energy-efficient as no operations have to be repeated due to mispredictions and speculation.
? ARM solves this issue by grouping load-words operations as much as possible to avoid stalls.
? If the LSU detects an unaligned data access, it issues first a request to the high word and stores the data in a temporary register.
? This has led to a design where the additional circuitry to support the vector operations did not have an impact on the overall operation speed.
? It avoids overly conservative prologue and epilogue insertion created by the auto vectorizer that are having a serious negative impact on code size.
• In the embedded domain, several solutions have been proposed in different technology nodes.
• A unique feature of the proposed SOC is the exploitation of body-biasing to reduce leakage power of the eFPGA fabric, achieving SOA state bit stream retentive sleep power for the eFPGA fabric.
• A vector can contain two 16 bit elements or four 8 bit elements. To perform signed and unsigned multiplications, the 8 bit/16 bit inputs are sign-extended.
• The proposed method performs better than pure random and manual approaches, as well as using a single test program that covers the highest coverage as proposed in.
• In the proposed MCU, they are used to store private CPU data such as the stack and instruction binary.
? Such DSPs achieve a very high performance when processing data, but are not as flexible as a processor and also harder to program.
? Therefore, we focus on building a micro-architecture based on the RISC-V instruction set architecture (ISA) which achieves similar performance and code density to state-of-the art MCUs based on a proprietary ISA, such as ARM Cortex M series cores.
? Performance can for example be increased with a dot-product instruction which accumulates two 16b×16b multiplication results in a single cycle.
? The system is designed for high performance computing and its power consumption is in the range of a couple of hundreds milliWatts and not suitable for IoT-applications.
? We compare the performance of basic RISC-Vimplementation to the architecture with the extensions proposed in this paper.
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