A 3 mW 6-bit 4 GS/s Subranging ADC with Subrange-Dependent Embedded References
ABSTARCT :
A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC’s input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC’s coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC’s fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC’s output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoMW) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.
EXISTING SYSTEM :
? High sampling rate (1-3 GS/s) ADCs with medium resolutions (6-10 bits) are utilized in diverse applications including wireless communication systems, ultra-wideband (UWB), direct-sampling TV receivers and digital oscilloscopes.
? Then, a concise overview of SAR ADC architectures is presented, as well as a review of some existing high-frequency ADC architectures.
? Towards the end, the proposed ADC architecture is introduced along with a description of system-level design aspects.
? Analog-to-digital converters (ADCs) are fundamental building blocks in electronic systems that process or store analog signals in the digital domain.
DISADVANTAGE :
? A potential problem of the two-step subranging architecture is the mismatch between the coarse and fine ADCs. The mismatches can be categorized as offset and gain errors.
? Another design issue of subranging ADCs arises from the reference voltage switching.
? The switching connection between the resistor ladder and the preamplifiers may lead to significant parasitic capacitance and slow down the circuit.
? As the device size goes down, the offset issue becomes unbearable in advanced CMOS technologies. In this design, the raw offset of the preamplifier-comparator combination reaches 25 mV, which is equivalent to 2 LSB.
PROPOSED SYSTEM :
• The proposed ADC architecture and associated design techniques described in this dissertation will assist designers to address some of the major challenges related to advancing the high-speed ADC state-of-the-art.
• Many timing-skew calibration techniques have been proposed in theory and have also been implemented on-chip or off-chip.
• Several techniques have been proposed to improve the speed of SAR ADCs.
• When designing the proposed hybrid ADC architecture for a particular application, the decision concerning the number of bits for the flash ADC and the CABS ADC should be made under consideration of power and area impacts.
ADVANTAGE :
? It also improves the performance of near-Nyquist operation since the preamplifiers and comparators need not experience large difference between two consecutive inputs.
? A two-step subranging architecture manifests itself in embedded systems due to the compact structure and power efficiency.
? Incorporating offset calibration and digital error correction techniques to further improve the performance, this work achieves greater than 5.2 effective number of bits (ENOB) and 40-dB spurious free dynamic range (SFDR) across the whole Nyquist band with only 30 mW.
? The high effective resolution bandwidth (ERBW) of 1.1 GHz facilitates its application in both Nyquist and sub-sampling operations.
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