Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization
Abstract : Aging-induced degradation imposes a major challenge to the designer when estimating timing guardbands. This problem increases as traditional worst-case corners bring over-pessimism to designers, exacerbating competitive and close-to-the-edge designs. In this work, we present an accurate machine learning approach for aging-aware cell library characterization, enabling the designer to evaluate their circuit under the impact of precisely selected degradation. Unlike state of the art, we bring cell library characterization to the designer, empowering their capability in exploring the impact of aging while protecting confidential information from the foundry at the same time.Furthermore, the fast inference of cell libraries makes it feasible, for the first time, to examine aging-induced variability analysis in a Monte-Carlo fashion. Finally, we show that the designer is able to select a less pessimistic timing guardband by choosing adequate delta threshold voltage ( \Delta {V_{th}} ) for their design and their needs. Our machine learning approach reaches an R^{2} score of >99\% for almost all data stored in the cell library. Only timing constraints show slightly less accuracy with an R^{2} score around 95%. When using ML-characterized libraries in static timing analysis, we achieve errors smaller than \pm 0.5\% and \pm 0.1\% for path delay and dynamic power, respectively. Errors in leakage power are negligible and even smaller by orders of magnitude. Our machine learning implementation for standard cell library characterization is publicly available. Download: https://opensource.mlcad.org
? Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits.
? Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow.
? In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower.
? As discussed above, aging adds new challenges to the existing timing analysis flow, as it complicates the simple variation model assumed by the modern timing libraries.
? As a possible solution, learning-based timing characterization is under active research.
? Our investigation revealed that the impact of aging is strongly dependent on the operating conditions of gates (i.e. input signal slew and output load capacitance), and not solely on the duty cycle of transistors.
? We further quantify the impact of aging on the degradation of image processing circuits.
? We explore the role of operating conditions of a gate/cell in determining the overall impact of aging in the scope of both timing analysis and logic synthesis – this holds even more for complex designs like processors.
? Targeting only a single OP C results in erroneously estimating the overall impact of aging on the paths of circuits.
• In order to predict a long-term dynamic NBTI effect, an updated model was proposed , which includes the recovery effect and is useful for the estimation of degradation by years.
• Two prevalent physical mechanisms, reaction–diffusion (R–D) and trapping–detrapping (T–D), have been proposed in the literature to explain NBTI.
• The authors of proposed a learning-based method for predicting the NBTI-induced delay degradation in large designs like processors.
• The obvious difference is that calculated the aged path delay using the LUT method, while our proposed method was a machining learning framework at the circuit path level.
• This paper proposed a novel learning-based aged delay prediction method at the circuit level.
? An equivalent contained guardband is computed as the performance penalty when synthesizing for aging by comparing the obtained CP delay against the CP delay of a traditionally-optimized version of the design synthesized with the initial cell library.
? In addition, logic synthesis can (also based on delay information within the targeted cell library) efficiently optimize the circuit’s netlist to maximize the performance.
? The high-performance 45 nm Predictive Technology Model (PTM) is used for both nMOS and pMOS transistors.
? During synthesis, the compile ultra option is used to optimize the designs along with the highest effort along with an objective of performance maximization.
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