Current-Bunch Concept for Parasitic-Oriented Extraction and Optimization of Multi-Chip SiC Power Module
Abstract : Parasitic inductance reduction is increasingly vital for the SiC power module in high-frequency and high-capacity applications. To address the parasitic issue, the automatic layout design offers the potential to pursue the optimal configuration of the power packaging. However, the efficient and accurate parasitic extraction of the packaging is the bottleneck of the automatic design scenario. In this letter, the current-bunch concept is proposed to achieve a tradeoff between the efficiency and accuracy of the parasitic extraction. The mathematical models are created to estimate the parasitics by using the proposed concept. Additionally, the challenge of abundant mutual-inductance caused by the multiplied power chips in the SiC power module is highlighted. Simulation and experimental results further demonstrate the advantages of the current-bunch concept. With the aid of the proposed approach, the packaging layout of a multichip SiC power module is optimized, and the parasitic inductance is reduced by 29.2%.
? Existing solutions for haptic feedback such as eccentric rotary mass (ERM) or linear resonant actuators (LRA) have a number of drawbacks.
? Existing manufacturer-owned solutions confirm that the need has been identified. At Power Design Technologies, we believe that only a third-party can make a difference for the designers.
? These drop-in replacement designs allow engineers to take advantage of these improved characteristics in both new and existing applications.
? Building on the company’s existing range of current sensor modules, this new and highly diverse modular technique leverages Hall-Effect and Rogowski sensors, as well as amplifiers and digital converters.
? Although the parasitic inductance of the power module itself is small, the voltage overshoot can be large if the parasitic inductance outside the modules are not decoupled.
? Adding decoupling capacitors on the module’s DC bus terminal side can effectively offset the parasitic inductances caused by external circuit layout.
? Therefore, in the module design stage, it is important to integrate decoupling capacitors in the module as well.
? In this design, a 7oz two-layer PCB with controlled thickness is used to solve this issue.
? The decoupling capacitors are easily soldered on a short laminated PCB bus bar and the PCB is closely soldered to the bus terminals of the power module.
• The proposed method is utilization of a tooled heat sink which accommodates both semiconductors and magnetics.
• Power semiconductors are mounted on the outer side of the heat sink, allowing for vertical MOSFET assembly, thus reducing PCB footprint.
• Magnetics are then potted using a thermal compound inside the slots of the heat sink.
• We proposed that although the coefficient equations can be big, provided that we know our analog poles and zeros and the switching/sampling frequency we can easily calculate them.
• The conventional LLC resonant converter was originally proposed as a solution to improve the efficiency of the DC-DC converter.
? Double-sided cooled module can effectively improve the thermal performance of the power module.
? However, thermal grease is required as heat spreader is used in the resin mold module thus limiting its thermal performance.
? At this initial design stage, only one SiC schottky diode is used as upper switch and one SiC MOSFET is soldered as the lower switch. Double pulse tests are performed to characterize the lower MOSFET’s switching performance and extract the module’s parasitic inductance.
? The parasitic inductance of two devices in parallel is to be extracted experimentally and compared with simulation results. Meanwhile, the characterization of the thermal performance and evaluation of thermal-mechanical stress for the new design needs to be studied as well.
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