Highly-Efficient Fully-integrated Multi-Voltage-Domain Power Management with Enhanced PSR and Low Cross Regulation
Abstract : Multi-voltage domains are urgently needed in modern SoCs, while existing solutions such as switched DC-DC converter, switched capacitor converter and low-dropout regulator (LDO) do not generate multi-voltage domains conveniently and inexpensively. This paper presents a highly-efficient fully-integrated power management strategy to provide the multiple voltage domains. The proposed architecture stacks a main LDO (MLDO) and several auxiliary push-pull regulators (APPRs) to generate multiple voltages for various loads in one SoC chip.The APPR regulates the load current by either absorbing or providing the additional current, which stabilizes the output voltages, increases the power supply rejection (PSR) and decreases the cross regulation (CR). A prototype with two output terminals is implemented with a standard 0.18-m CMOS technology. The whole system achieves high power efficiency of 96.5% and high PSR of - 62 dB and - 142 dB for upper and lower outputs, respectively. The chip area is 980 m 500 m and the total quiescent current is 239 A. In addition, all off-chip components are eliminated, which is favorable for monolithic realization. The reduced system cost and the reduced electromagnetic interference (EMI) also simplify the power management significantly, which helps to enable low-power and compact SoCs.
? At the same time, every power saving technique introduces an overhead in terms of area and design complexity, as well as an overhead in terms of energy and time required to recover back into active mode.
? Consequently, there exists a penalty for the implementation of a power saving technique, as well as a penalty for activating it.
? There hence exists a penalty for the implementation of these techniques, as well as a penalty for activating them.
? The most efficient strategy for leakage avoidance is to switch-off the MCU digital core, either completely or partially
? A large capacitor at output node reduces undershoot/overshoot, but it increases silicon area and output voltage settling time.
? Depending on the load range, and the type of digital control used, a wide bandwidth DLDO control loop can reduce both undershoot/overshoot and settling time.
? However, it is challenging to design wide bandwidth DLDO linear control loop due to load dependent stability issue.
? However, the ALDOs suffer from stability problems due to load dependent output pole and the need for complex compensation networks
• Among many other proposed techniques, the most effective approach to minimize the leakage current is to switch-off the MCU digital core, either completely or partially.
• In the proposed ultra-low-power MCU system, the digital core is supplied by a linear low-dropout voltage regulator (LDO). Conventionally, such an LDO is stabilized by a large external capacitance at its output, which is at least in the range of some 100 nF.
• The most widely proposed approach is to interpose a buffer stage between the error amplifier output and the pass-transistor gate node.
? The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art.
? By having a good PSR performance, the proposed DLDO is able to power mixed signal load.
? To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller.
? In , a coarse-fine dual loop control (coarse control loop operating at fast clock and fine control loop operating at slow clock), is used to improve the trade-off between transient performance and DC accuracy. However, the dual loop control increases the complexity of the DLDO.
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