WiDir A Wireless-Enabled Directory Cache Coherence Protocol
Abstract : As the core count in shared-memory manycores keeps increasing, it is becoming increasingly harder to design cache-coherence protocols that deliver high performance without an inordinate increase in complexity and cost. In particular, sharing patterns where a group of cores frequently reads and writes a shared variable are hard to support efficiently. Hence, programmers end up tuning their applications to avoid these patterns, hurting the programmability of shared memory. To address this problem, this paper uses the recently-proposed on-chip wireless network technology to augment a conventional invalidation-based directory cache coherence protocol. We call the resulting protocol WiDir. WiDir seamlessly transitions between wired and wireless coherence transactions for a given line based on the access patterns in a programmer-transparent manner. In this paper, we describe the protocol transitions in detail. Further, an evaluation using SPLASH and PARSEC applications shows that WiDir substantially reduces the memory stall time of applications. As a result, for 64-core runs, WiDir reduces the execution time of applications by an average of 22% compared to a conventional directory protocol. Moreover, WiDir is more scalable. These benefits are obtained with a very modest power cost.
? While many variations of these coherence schemes exist in the literature, they have typically been described at a rather high level, making adequate evaluation difficult.
? Ail of the information needed to determine whether a given writebuck command should be discarded exists in the directory bits.
? The only cryptic notation in this column is (add), which means the valid bit corresponding to the pointer that is becoming valid should be turned on (“added”) in the existing state.
? Perhaps the simplest solution using the existing datapath is to delay the reply to exclusive commands until all of the invalidate commands have been sent.
? In this paper, we focus on a different problem: enlisting both NoCs in supporting cache coherence protocol transactions.
? To address this problem, this paper uses the recently-proposed on-chip wireless network technology to augment a conventional invalidation-based directory cache coherence protocol.
? To gain insight into this issue, we modeled writes that update rather than invalidate, and measured the number of sharers that a line accumulates until the line is evicted from the LLC.
? It is possible that one of the sharer nodes now issues a write (now using the wireless data network) before the initiating directory has fully terminated the ToneAck operation.
• Several possible models have been proposed, e.g., strong ordering, weak ordering, release consistency, etc.
• The purpose of this paper is to clarify these notions by presenting a reasonably detailed design of the hardware needed to implement a directorybased cache consistency protocol.
• The purpose of the directory controller is to process C+MM commands, we could not design it until those commands were defined.
• The purpose of the invalidation, of course, is to limit the number of cached copies to three so that the caches’ processor numbers can be stored in the three pointers.
? An intriguing question is whether a conventional, wired cache coherence protocol can be augmented to use a wireless network so that patterns like the ones described above can be supported efficiently.
? A similar support has been proposed by TLSync and WiSync for efficient core synchronization.
? If programmers want to attain high performance, they have to carefully tune the sharing behavior of their applications, ensuring that patterns like the ones mentioned appear infrequently.
? WiDir, instead, not only allows the directory to scale without domain restrictions, but also boosts performance by enabling broadcast updates of highly-shared lines.
? Coherence protocols rely on invalidations to keep coherence and do not support these patterns efficiently.
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